Microblaze problem after adding IP

This might sound familiar if you have read any of my previous posts but I don't have long to get this working and I haven't worked with these for very long.

I have a working Microblaze build that uses FSLs to communicate with external hardware through a custom module. The design works as I expect but adding another IP causes problems.

At first I thought that adding more FSLs was creating a problem but it seems that adding any IP has the same effect.

I wrote a small clock divider module, tested it and imported it into a working MB project. This module requires no software and no interaction from the CPU. It is only connected to the internal system via the sys_clk_s and to an external pin.

The divider is working as I see it on my 'scope now but I can't debug when this module is present (it seems the CPU is stuck or hung). The Bootloop is marked for BRAM initialisation and I'm putting the main program into RAM at 0x44000000, I made the recommended RAM controller modifications to get this to work in the first place (although I don't know whether this is the same issue).

It works -> I add the clock divider -> It doesn't work, would be the basic problem flow .

Someone must have experienced this before? Maybe something to do with the DDR RAM?

EDK 9.1.02i
Spartan 3E500 Starter kit

Many thanks,

Rob

I can only offer the following: Contact your local Xilinx FAE if this is a work related project and if not then start a webcase on the Xilinx website.

E

I've asked on their forums as well.

It's project related at present but it is also likely that I will work with FPGAs in the near future, the company I will work at has also had problems with Xilinx tools.

I can't think of why adding such a simple peripheral affects the system like this. I'm trying another couple of builds using different memory options (MCH OPB and Flash). I keep thinking it is memory related but like most problems I've had with this it has been the last thing I suspected.

Are you using the recommended device with that particular piece of IP? Have you changed any of the contraints that are or could have been specified for the IP? Have you just instantiated it or did you attempt to do any floorplaning and such?

E

As far as I know (yet!) I have solved the problem .

It seemed somewhat erratic behaviour with the uC, especially after just adding a basic part to the build. I still can't explain why it happens.

I dug into it for a while and found that both the v1.00.c and v1.00.b mch_opb_ddr controllers don't seem to work nicely with the Micron MT46V32M16-6T memory part on my RevD starter kit. The revision "a" controller seems to be OK but I haven't tried it without the phase shift and extra constraints, I might just to see what happens.

I don't know if that is general knowledge or not and I might just be catching up with everyone but I only started with MicroBlaze lately.

Hopefully it will remain stable when I add the FFT core today!

A little background, the IP was written by me and it was only a clock divider for an external device. The build was a MicroBlaze with my custom FSL peripheral (ADC reader, 1-deep FIFOs) and that worked but as soon as the new divider bit was added the debugger was hanging or the memory test was failing.

I just built the whole thing with two FSLs, one for the ADC and one for the FFT core and it's still working. Hopefully it will continue to do so while I fill some large arrays in SDRAM .