Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

what is the maximum frequency?

Status
Not open for further replies.
S

samiksha

Junior Member level 1
Joined
Jan 3, 2008
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,397
i'm comparing four multipliers for delay,area nd power. wht shud be the max frequency to be given as design constraint for good performance of the multipliers. i'm using Xilinx9.2 nd comparing array,modified booth,wallace tree nd combined booth wallace
waiting for ur valuable suggestions
thanx:|
 

Max frequency should be based on your timing budget and should be reasonable based on the rest of the design.
 

max frquency is given by 1/max tclk.
 

max frequency of operation is based on the critical path violations
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top