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Counter acting really strange - help is needed.

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ohadohad2

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Hello everyone, I wonder if anyone can explain why I seem to get the same error over and over.

So I was writing a code and a part of it was a counter.

After I completed writing the code I noticed that the count seem to act very strangly, for some reason the counter output seem to change mid clock although its clock edge triggered.

To check this I used VHDL waveform file.

Here are some diffrent codes I wrote for the exact counter and all seem to have the same problem (Im also attaching a picture of one of the timing simulations):

entity Counter is
generic (N : integer := 7);
port(enable,clk,rst:in bit;
Count:eek:ut integer range 0 to N);
end Counter;


architecture Counting of Counter is

type Count_State is (Zero,One,Two,Three,Four,Five,Six,Seven);
signal Current_State: Count_State;

begin
process(clk,rst)
begin

if rst='1' then Current_State<=Zero;
elsif clk'event and clk='1' then

case Current_State is

when Zero => Current_State<=One;
when One => Current_State<=Two;
when Two => Current_State<=Three;
when Three => Current_State<=Four;
When Four => Current_State<=Five;
when Five => Current_State<=Six;
When Six => Current_State<=Seven;
when Seven => Current_State<=Zero;
end case;
end if;
end process;

with Current_State select

Count<=0 when Zero,
1 when One,
2 when Two,
3 when Three,
4 when Four,
5 when Five,
6 when Six,
7 when Seven;

end Counting;







----------------------------------------------------------------------------------------

entity Dflop is
port(D,rst,clk,enable:in bit;
Q:eek:ut bit);
end Dflop;

architecture Behave of Dflop is
begin
process(clk,rst)
begin

if rst='1' then
Q<='0';

elsif(clk'event and clk='1') then
if enable='1' then
Q<=D;
end if;
end if;

end process;
end Behave;

----------------------------------------------------------------------------------------

entity Struc_Counter is
generic (N : integer := 7);
port(clk,rst,enable: in bit;
Count:eek:ut integer range 0 to N);
end Struc_Counter;

architecture Struc of Struc_Counter is

component Dflop
port(D,rst,clk,enable:in bit;
Q:eek:ut bit);
end component;
----------------------------------------------------------------------------------------

signal inA,inB,inC,outA,outB,outC: bit;
signal ABC : bit_vector (0 to 2);

begin

inA<=((outA and (not outB)) or (outB and (outA xor outC)));
inB<=(outB xor outC);
inC<=(not outC);

A1:Dflop port map(D=>inA,rst=>rst,clk=>clk,enable=>enable,Q=>outA);
B1:Dflop port map(D=>inB,rst=>rst,clk=>clk,enable=>enable,Q=>outB);
C1:Dflop port map(D=>inC,rst=>rst,clk=>clk,enable=>enable,Q=>outC);


ABC<=outA & outB & outC;

with ABC select

Count<= 0 when "000",
1 when "001",
2 when "010",
3 when "011",
4 when "100",
5 when "101",
6 when "110",
7 when "111";

end Struc;



entity Counter is
generic (N : integer := 7);
port(enable,clk,rst:in bit;
Count:eek:ut integer range 0 to N);
end Counter;


architecture Counting of Counter is
signal cnt:integer range 0 to N;
begin
process(clk,rst)

begin

if rst='1' then cnt<=0;

elsif (clk'event and clk='1') then
if enable='1' then
cnt<=cnt+1;
if cnt=N then
cnt<=0;
end if;
end if;
end if;

end process;

Count<=cnt;

end Counting;
 

i think you should consider the hardware delayed time, although it's a clock triggered design, but every signal inner Fpga has different routing ,so you get a not-so-pretty waveform.
 

pwq1999 said:
i think you should consider the hardware delayed time, although it's a clock triggered design, but every signal inner Fpga has different routing ,so you get a not-so-pretty waveform.

I'll look into it, although I even ran the system at very low frequencies and its still jittered like that :(
 

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