raka200
Member level 2
Hi everybody
I have a test bench in vhdl that I run under modelsim XE starter.
I 'd like to write to a file some signal. I have modified the test bench, but the simulation time as increased dramatically (x100 !!!)
Is there a way to speed up the simulation ??? (using buffer, other text function ???)
Here is my piece of code :
thank in advance !!!
I have a test bench in vhdl that I run under modelsim XE starter.
I 'd like to write to a file some signal. I have modified the test bench, but the simulation time as increased dramatically (x100 !!!)
Is there a way to speed up the simulation ??? (using buffer, other text function ???)
Here is my piece of code :
Code:
library STD;
USE STD.textio.ALL;
file MyFile : text open write_mode is "C:\FileOut.txt";
constant SEPAR : string := " ";
WriteToFile : PROCESS(CLK)
variable MyLine: line;
BEGIN
if rising_edge(CLK) then
write(MyLine,conv_integer(FirstVector),left,1);
write(MyLine, SEPAR, left, 1);
write(MyLine,conv_integer(SecondVector),left,1);
writeline(MyFile ,MyLine);
end if;
END PROCESS;thank in advance !!!