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using LVDS pins as single ended, is it reasonable?

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vahidkh6222

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hi,
Is it ok to use one pin from differential LVDS pairs as single ended.
I need to provide an external single ended clock for the DAC eval board.
my fpga is vx4sx95.
 

Normally, LVDS ist just one of many IO standards selectable for an FPGA pin respectively pin pair. You should be able to set it to e. g. 2.5V CMOS. Operated as LVDS, the output voltage may only be sufficient for an AC coupled clock input.
 

Hi,

can u pls explain me "Common Mode Voltage" at the receiver in LVDS?

THanks
 

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