DDR SDRAM controller operation and Virtex2 Pro

ddr sdram controller pdf

Hello,

i am reading now about DRAM modules, and see that SPD (serial presence detect) function is implemented in their EEPROMs. i can easily find datasheed for Micron device... but cannot find datasheet for any other device..

so the question is: Does the operation and the organization of burst data read/write process differs much between diffferent manufacturers of RAM chips? (if they all use I²C bus... then it must be same...no?)

i am going to use DDR SDRAM controller, and of cuz using of the already written PLB DDR SDRAM controller soft IP from Xilinx will be faster than writing yours from scratch. Anyway i am going to read more in order to understand it better.

but the next question is: where to get the VHDL code for the PLB DDR SDRAM controller from Xilinx? (ds425) i can find PDF datasheet.. but not VHDL code with comments...

and what is the difference between single rank DDR controller and dual rank DDR controller? (i have these options in BSB in EDK during the selection of peripherals)

thank u.

virtex2pro + ddr controller + ise

As far as I understand, the present Xilinx solution is MIG (memory interface generator), that is said to generate unencrypted HDL code. (Don't know if also generates code comments?)

ddrsdram interface to virtex2 pro

ISE 9.1 has also MIG 1.7, but it apparently doesn't support Virtex II. But if you generate the controller with EDK, what do you get? Does it generate readable HDL code respectively reference readable HDL code in a library, or encrypted HDL? If it's plain HDL, it must not be easily understandable anyway, probably lacks of comments.