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Timing constraint violations when crossing clock domains?

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davr

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Hi,

I'm building a project which has two main clock domains inside it (100MHz and 65MHz), and there are several places where signals will cross back and forth. I use this method of passing the signals between domains:
Code: 
dataA : IN std_logic;
clockA : IN std_logic;
dataB : OUT std_logic;
clockB : IN std_logic;
-- ...
signal buffer : std_logic;
-- ...
process(clockB):
begin
  if(rising_edge(clockB)) then
     dataB <= buffer;
     buffer <= dataA;
  end if;
end process

However, when I specify a global timing constraint (65MHz for my one clock, 100MHz for my other clock) I get lots of errors for the paths that cross between, eg dataA->buffer->dataB would complain.

I found I can tell it to ignore (false-path) all signals that cross from one clock domain to the other, but I'm not sure if this is the best approach. Does anyone have any suggestions? Thanks.
 

yes, just set the path as false path will done the job
 

Re: Timing constraint violations when crossing clock domains

hi,
Set the path to multicycle path.

Thank you.
 

Re: Timing constraint violations when crossing clock domains

dataA : IN std_logic;
clockA : IN std_logic;
dataB : OUT std_logic;
clockB : IN std_logic;
-- ...
signal buffer : std_logic;
-- ...
process(clockB):
begin
if(rising_edge(clockB)) then
dataB <= buffer;
buffer <= dataA;
end if;
end process
Click to expand...

Your sample code here doesn't take the input data clocking at "clockA"@100MHz....There seems no sync or handshake between your two clk domains..This definitly will lead to data missing...I too have experienced a lot from this issues....You must take the source clk into account. Or else,use an indepth FIFO logic...I had my problem of CDC(clk domain crossing) solved by simply buffering the data before sending...Mind to keep the buffer size pretty big...As there is always a solution,no matter how fast a clk is,simply add buffer stages between two! with ofcourse some tmming issues in mind!...All the best
 

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