What's wrong with my VHDL code

unexpected architecture, expecting semicolon

Hello friends,
I am doing a very basic design in VHDL. i am simply designing a ROM of 8 rows and each row of 4 bits in width. Can anyone help me in correcting my code. I am getting the error

ERROR:HDLParsers:164 - "H:/vhdl_practice/ROM_Exapmle.vhd" Line 9. parse error, unexpected INTEGER_LITERAL, expecting SEMICOLON or CLOSEPAR


Here is my code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rom1.ALL;


entity ROM_Exapmle is
port (address_in : IN integer 0 to 7;
data_out : OUT std_logic_vector(0 to 3));
end ROM_Exapmle;

architecture Behavioral of ROM_Exapmle is
signal RO : memory;
begin
data_out <= RO(address_in);

end Behavioral;

and the package code is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


package rom1 is
type memory is array(7 downto 0) of std_logic_vector(3 downto 0);

end rom1;



i corrected the code by putting the semicolon. But i am getting the same error message.

The line which as the error is port (address_in : IN integer 0 to 7;



pls help me friends

Thanks and Regards
Deepak

vhdl semicolon

correct me if i'm wrong, but don't you need a 'range' keyword in there?

vhdl wrong index type

Hi friend,
I tried without giving the RANGE keyword. But i am getting the same error message....

Thanx and regards
Deepak

Added after 24 minutes:

ok friends,
Thank you very much. I got the synthesis sucessful

i got code wrong i need code for zero hour

deepu_s_s said:

ok friends,
Thank you very much. I got the synthesis sucessful

Click to expand...

Oh oh ooh!...That's ok friend, but could you just tell what correction in that has solved you?....It could help many people here to understand the error synthesis!...Thanks

vhdl unexpected semicolon

everything is correct my friend, i didnt put a semicolon