How to make a big delay in VHDL code?

VHDL starter question

hello out there
how can i make a big delay like 1,10,15 sec
for example if i want my output to go high after 10 secs from the incoming signal on my input ???
should i make counter module ??
Need some guide and some coding example if posible
thx

you should use the counter to deviding your clock core. The devided clock will be used to enable the latch of your signal

i think you should delaying your signal by FPGA!!!

if you want to change the clock domain, i think you should be used a FIFO

Re: VHDL starter question

Hi,

There are ways to delay a signal in behavioural code using the 'after' reserved word. I guess you are interested in delaying your signal in your RTL, in that case you need a counter.

If you have a 20MHz clock and you want to delay a signal by 10 seconds you need a big counter, doable but big...a 28 bit counter or something like that. If your master clock is slower than that, let's say 1KHz then smaller counter...

I hope it helps
-maestor

"after" reserved word is only use in testbench!

Re: VHDL starter question

Hi hienpv,

'behavioural code'=code you use in your testbench, it could be synthesizable or not and clearly after is not.

RTL is the notation we use for synthesizable code in general.

-maestor

The keywords "after" is used in RTL simulation only,and after synthesized,it will be abort.
If you want to realize delay in design,use counter will be good way and it will use some register. the more delay,the more need to be used!

i will use a 1 sec delay counter and multiply that by how many seconds i want the output to be delayed .
the problem that im thinking of is that i have to make as much couters as much outputs that i have ,is that right?
What do u think guys ?

Re: VHDL starter question

if you want to change the clock domain, i think you should go for a FIFO

Re: VHDL starter question

it depends on if you are doing synthesizable code or not

Re: VHDL starter question

Dear Zelc

the shown code I wrote to implement digital monostable behavioral. you can use your input signal to trigger it and use its output in place of the delayed signal

Al Faouk

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

Entity Done_Sim is
port(
Rst : in std_logic;
CLK : in std_logic;
Load : in std_logic;

Done: out std_logic

);
end Done_sim;

architecture Sim of Done_Sim is
signal counter : integer range 0 to 65535;
signal Load_pulse: std_logic;

begin
single_pulse: process(Rst, Clk, Load)
variable decide : std_logic_vector(1 downto 0);
begin
if rst = '0' then
decide := "00";
else
if rising_edge(clk) then
decide(1) := decide(0);
decide(0) := load;
end if;
case decide is
when "01" =>
load_pulse <= '1';
when others =>
load_pulse <= '0';
end case;

end if;
end process;

One_Shot: process( Rst, Clk, Load_pulse)

begin
if Rst = '0' then
counter <= 0 ;
done <= '0';
else
if rising_edge(clk) then
if load_pulse = '1' then
counter <= 65535;
done <= '1';
else
if counter = 0 then
done <= '0';
else
counter <= counter - 1;
done <= '1';
end if;
end if;
end if;


end if;
end process;

end;

Re: VHDL starter question

if your design has a processor core, better use software to do it.

Re: VHDL starter question

One smart and logic efficient way I've seen to divide clock by a huge amount is to use LFSR. You can search xilinx app for this topic.

regards