Help me choose the baud rate divisor value for this code

i am using spartan 3e ... i try to communicate with the pc by using serial communication ..... i use 50 mhz clk ..... i want to get 9600 baud rate to send a 8 bit register .... what is the value of the divisor should i take ..... i used 5208 for the divisor also i tried 1302 but i don't recive anything at the hyberterminal ?!!!!!! whatshould i do


i made this code

itried this code in the simulator and i get a true output by usind divisor= 5 to notice the output so i think the error will be in the baud rate


c is the clock
y is the tx

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY cout IS
PORT(
c : IN std_logic;
rst : IN std_logic;
y : OUT std_logic
);

-- Declarations

END cout ;

-- hds interface_end
ARCHITECTURE muha OF cout IS
signal tm:std_logic_vector(15 downto 0):=(others=>'0');
constant div:integer:=5208;
signal clk:std_logic;
signal busy:std_logic:='0';
signal mess:std_logic_vector(9 downto 0) :=(others=>'0');
signal cout:std_logic_vector(15 downto 0 ):=(others=>'0');
BEGIN
clkgenrocess(rst,c)
begin
if rst='1' then
tm<=( others=>'0') ;
clk<='0';
elsif c='1' then
clk<='0';
if tm=div then
tm<=(others=>'0');
clk<='1';
else
tm<= tm + 1;
end if ;
end if ;
end process;
shifrocess(c)
begin
if busy='0' then
mess<="0111010111";
busy<='1';
elsif ( busy='1' ) then
if (clk='1'and c='1') then
y<=mess(9);
mess(9 downto 1)<=mess(8 downto 0 );
cout<=cout + 1;
end if;
end if;
if cout=20 then
busy<='0';
cout<=(others=>'0');
end if;
end process;
END muha;

baud rate divisor

I can't identify a clock divider in your design, it has no edge sensitive expression in the process. Either rising_edge(c) or (c'event and c = '1') would be needed to make up a counter respectively clock divider.

Compare with a UART design as

Re: baud rate divisor

i use instead of rise edge the condition of c=1 and clk =1

baud rate divisor

That is not an "edge" condition, that is a "level" condition.

Because of what's NOT listed in the sensitivity lists, you will have a number of warning messages in the synthesis report, that tell you the simulator will not simulate what the tools will generate.

Re: baud rate divisor

yes it is a level condition but it have a nother condition that make it like edge condition , it is becouse " process(c) " that make the process run only when the change of the clock c done . so it generate similar ...


and i am sorry for all of that becouse i discover that the fault was not in the code
it was in the cable

i did a mistake by using "UNCROSSED" cable instead of cross cable . i thought it was cross but when i test it i find it is not

thanks all for your time

Re: baud rate divisor

If the design is working that way, it would be really strange: The clock counter is build from latches instead of flip-flops. It could be, that the Xilinx tool has an option to turn latches into flip-flops, otherwise I can hardly imagine how it should divide the clock correct. But that shouldn't be my problem.

Re: baud rate divisor

Ok,

I recommend you to map your buadrate clock (Y) on an unused pin of fpga and then check it by oscope. If it's not as you need try to change your design until you get what you need. Before getting a good clock don't start working on others part of design.

But it is obvious that your code doesn't work until you add a clock edge condition to your code. i guess you confused and you thinking like verilog not VHDL. In VHDL clock edge condition is necesary. otherwise it doesn't work.

Re: baud rate divisor

The design also wouldn't work in Verilog, cause an always @(c,rst) together with a (c==1) condition infers a latch. But the syntax actually is very different in this regard. I wonder, if Xilinx has also templates that suggest a basic structure for synchronous designs as Altera has. Basically you should have something like this:

P.S.: I attached an operational n,8,1 UART Tx example

Re: baud rate divisor

i didn't try the code you gave to me , but this is the simulation of my code using modelsim in mentor graphics software and it is the same at ise8.2 simulator

i make 2 simple difference but it is not real difference .... i put intial value to y='1'
and make divisor=2 to notice the change

you will notice that it divided by 3 becouse the condition i put in the code

i will try your code to improve my design

i am not professional in vhdl , at first i tried to make the code using edge condition but it didn't work in the simulation ... so i ask my self what is the meaning of process(a,b) it mean that the process will run whaen a change in a or b occure
so it can be instead of rise edge but at first time i made that it make shift by 2 number when i looked at the simulation i see that in make it at rise and fail edge of the clock generated so i put another condition that c='1' to make it shift one time each clock

i think i move from a problem to another since i begin this but i will try to solve them all , thanks for your interest [/img]

Re: baud rate divisor

i didn't try the code you gave to me , but this is the simulation of my code using modelsim in mentor graphics software and it is the same at ise8.2 simulator

i make 2 simple difference but it is not real difference .... i put intial value to y='1'
and make divisor=2 to notice the change

you will notice that it divided by 3 becouse the condition i put in the code

i will try your code to improve my design

i am not professional in vhdl , at first i tried to make the code using edge condition but it didn't work in the simulation ... so i ask my self what is the meaning of process(a,b) it mean that the process will run whaen a change in a or b occure
so it can be instead of rise edge but at first time i made that it make shift by 2 number when i looked at the simulation i see that in make it at rise and fail edge of the clock generated so i put another condition that c='1' to make it shift one time each clock

i think i move from a problem to another since i begin this but i will try to solve them all , thanks for your interest

Re: baud rate divisor

I can't see from the ModelSim wave if the design is operating correctly, tm seems to count with a divisor of 4, I fear, that in a real FPGA or a timing simulation, it wouldn't count regulary at all, for the said reasons.

Basically a process sensitivity list doesn't assure, that the code is evaluated at an edge only, VHDL has 'event attribute respectively rising_edge()/falling_edge() function to achieve this. A flip-flop or a counter won't be generated without using this construct, you can consult any VHDL textbook.

Re: baud rate divisor

ok , i will rebuild my design based on that
but what about this code
do you think i can use it , it work in simulation but i didn't use it yet in real time

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY count IS
-- Declarations
generic(delay :time:=104166.6666ns);
port(clk :in std_logic;
y ut std_logic);
END count ;

-- hds interface_end
ARCHITECTURE behaviour OF count IS
BEGIN
process
begin
wait for delay;
y<='1';
wait for delay;
y<='0';
end process;
END behaviour;


also we can use frequency in generic