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Xilinx Modelsim post-simulation error

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xie.qiang

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hi, when I run post simulation on Modelsim, it report the erro infor about this, can you guys help me?

# ** Error: C:/Modeltech_6.3d/xilinx_libs/simprims_ver/simprims_ver_source.v(17175): $recovery( negedge RST:994435 ps, posedge CLK &&& (rst_clk_enable1 == 1):995219 ps, 798 ps );
# Time: 995219 ps Iteration: 2 Instance: /tb_dds_32x16_top/u_dds_32x16_top/\u_sys_rst_gen/mst_rst_r0

And attachment is the wrong wave as well as the wrong code reported by modelsim.

Thanks.
 

Re: Xilinx Post-Sim Help

I have solve the problem, it's because the recover of reset before clk posedge time does not match the SDF(standard delay file), modify the reset stimus, it works ok now.

Anyway, thans you guys care.

Regards,

Chris
 

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