How to generate a snyc clk from a non-periodic SQR?

Hi friends!, I have an issue upon demodulating ASK waveform from my ADC...I have attached a pic that best describes all....I transmit the ASK modulated sine wave from DAC of my transmitter and receive it in ADC of my reciever.In turn this peripherls will be connected to FPGA(virtex 4). Here I have succesfull generated ASK and have transmitted and whilst receiving,I need to recover the data from the ASK waveform. So I have performed a schmit trigger operation in FPGA to convert the ASK sine wave to SQR wave as shown in the fig. Then I must generate a ref clk purely generated based on the sqr pulse obtained from the sine...Because I recover my data by sampling the sine wave with this recovered clk,so that for each rising edge,I will check if the sine values are greater than 0,if so then I consider it as 1 and if the ask is dead(For '0' data-OOK type)then I consider it as '0' in the receiver....For these operations if I use the sampling clock generated by the divider counter values of the receiver FPGA,then theso generated clk and the ASK SQR doesn't sync.Because the ASK sine and sqr are from Tx domain and the sample clk generated is from Rx domain...So could you guys suggest me a solution upon how to generate the sample clk(like the clk I have drawn in diagram) with sync on the ASK sqr pulse....Thanks in advance