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Help me convert VHDL code to Verilog

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mondobongo

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how can i convert this code to verilog...
I didn't understand...

process (Reset,Clk)
variable RegBit :integer range 0 to 13;
begin
RegBit := conv_integer(BitCountPar);
if (nReset = '0')then
Data <= '0';
elsif (Clk'event and Clk = '0')then
if (EnableStrobe = '1')then
Data <= DataReg_ss(13-RegBit);
else
Data <= '0';
end if;
end if;
end process;

Thanks

Added after 1 hours 20 minutes:

please urgent help needed
 

Re: vhdl to verilog

For a quick (but non-elegant) solution, you can use XHDL to convert VHDL codes into verilog.
 

Re: vhdl to verilog

Code: 
// here i assume DataReg_ss is memory declared as
// reg [N:0] DataReg_ss[0:13]
// and 0 =< BitCountPar =< 13
always @(negedge clk or negedge reset_n) begin
    if (!reset_n)
      data <= 0;
    else
       if (EnableStrobe)
           data <= DataReg_ss[13 - BitCountPar];
       else
           data <= 0;
end
 

Re: vhdl to verilog

thanks nand_gates
so
I don't have to convert a register to an integer to use in bracket in verilog
but in vhdl i have to
 

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