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How to convert 'real' values to std_logic_vector ?

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GeekWizard

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vhdl math_real std_logic_vector

Is there a way to convert real values to std_logic_vector format?

The conv_std_logic_vector() apparently only takes in integer values and gives an error for others !

Many Thanks.
 

convert unsigned to std_logic_vector

First of all, what kind of treatment do you want for non-integer numbers?

The real number 5.25 should become what bit pattern?
00000101 for 5?
00010101 for 21 quarters (expressed with the LSB being one quarter unit) ?

In any case you should use ieee.numeric_std.all, and use to_unsigned. You can cast the real to integer if you just want to take the integer part

my_sig <= to_unsigned(integer(5.25),my_sig'length);
 

    GeekWizard

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convert real to std_logic_vector

1. Real arithmetic and type conversion implying real isn't handled by IEEE.NUMERIC_STD package rather than IEEE.MATH_REAL.

2. Converting real to integer requires IEEE.MATH_REAL round() function. E. g.:
Code:
CONSTANT UREF: INTEGER := ROUND(1.23*2.0**15);
3. For synthesis, real mathematics is available for compile time operations only, e. g. for calculating constants or generation of ROM tables. Runtime float operations requires floating point cores.
 

convert real to std_logic_vector

Heres my problem:

1. 'integer' is only 32 bits. I am working with numbers greater than that uptil 48 bits. (e.g. 4.456E13)

2. My idea was to use 'real' numbers for all computations and then convert them to a std_logic_vector of 48 bits to output ports.

So its not the floating point numbers that I'm worried about. Any idea how to get around this problem ?

Thanks !

Added after 2 minutes:

On a side note, is there an ALU unit in the Quartus compiler? I have looked through the available 'symbols' in the library and could not any such component.
 

vhdl cast real to integer

Signed or unsigned arithmetic, that can be used for synthesis, isn't limited to 32 bit (although some IP, e.g. Xilinxs divider core has an arbitrary 32 bit limitation). I mentioned integer type only to demonstrate usage of IEEE.MATH_REAL in synthesis. Also floating point could be used - with special IP. opencores.org has some float stuff.

Altera in particular has FP_ADD_SUB, FP_MULT, FP_DIV, FP_SQRT and FP_COMPARE Megafunctions shipped with Quartus.
 

real in std_logic_vector

I opted to work with all 'unsigned' type numbers and I'm getting an error in using "/" (division) operator !

Error (10327): VHDL error at computation2.vhd(90): can't determine definition of operator ""/"" -- found 0 possible definitions

What does this mean ?
 

convert real to std_logic_vector

Dividers aren't infered from "/" operator in most synthesis tools.
 

vhdl std_logic_vector type conversion

So how should dividers be implemented in VHDL for Quartus?

The thing is Quartus compiler was inferring the "/" operator as a divider when the numbers involved were integer types but not for unsigned !
 

math_real vhdl real to integer

I don't think that Quartus infers dividers with integer type (or I wasn't aware of the feature yet). It can evaluate "/" operator in constant expressions or for compile time calculations. But for synthesis purposes, you have to use alt_divide Megafunction or any other divider core, you supply.

P.S.: I found, that Quartus actually infers dividers from integer divisison. However, the feature is effectively undocumented in Quartus handbook. I have to learn, if the divider parameters can be conrolled in a useful way. Thank you for this interesting insight.

P.P.S.: We can define the operand size by INTEGER RANGE settings, also >= 0 subrange is treated as unsigned operand. But seems to work with INTEGER type only.
 

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