Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Unnecessary transitions on single bit outputs

Status
Not open for further replies.
N

Nikolai

Member level 3
Joined
Jun 24, 2007
Messages
62
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,879
I have designed an FSM with generates output signals (single bit).

The problem is, the outputs are undergoing transitions (picosecond wide transitions) even when i am not intending it.

Im attaching my code,testbench, and a screenshot of the post PAR simulation.

As you can see, outputs are undergoing very small transitions, when they ought to remain stable. What is cause of such behaviour.

Can anybody help ?
 

The output signals are generated by decoding current_state in combinational logic, glitches can possibly occur due to different logic delays. Picoseond glitches should not be expected to appear actually at a hardware pin. But to assure glitch free operation of decoded ouputs from FSM without depending on special logic family features, the signals should be registered to my opinion.
 

Can u plz elaborate on how to register a signal...

du mean store it in a register ?
 

A registered signal would be implied, when assigning the output in a clock synchronous process, e. g. together with assignment of current_state. But this results in a delay of one clock cycle. Otherwise, you would need a decoder in clock synchronous process driven by next_state. But I don't know your design requirements, you should be able to find a solution considering the behaviour of combinational and clock synchronous logic.
 

The outputs of the FSM, are actually async reset signals to other modules.. Since they are async, i cannot afford the glitch. Also i cannot afford the delay of an extra clock cycle.
I guess, if i change the resets to synchronous resets, it might solve the problem.
 

Yes, I think so. Additionally, an asynchronous reset always implies a risk of getting undefined states in the resetted entity, if release of reset coincides with next clock edge.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top