1Hz clock source for CPLD

xc9536 pinout

Hi folks,

I am working on a simple 7 segment clock project using a XC9536 CPLD by Xilinx. I have some experience with microcontrollers but this is the first time I will be using a CPLD so please be gentle

To generate the timebase I figured the easiest option would be to use a standard 32.768kHz watch crystal and divide it to acquire the 1Hz however I am slightly confused by the pin assignments for the external clocks. On a simple microcontroller system I would just use the OSC1/OSC2 pair to hook up the crystal but I couldn't see a similar arrangement in the pinout descriptions for the XC9536. To add to my confusion, I have found this bit of circuitry and I can't make any sense out of it:
**broken link removed**

A NAND gate?? Can't I just use the crystal on it's own? (with loading caps)

The other problem is how do I actually divide the clock? I am planning to use VHDL so would it be simply "wait for 1ns" between my instructions?


I am slightly confused and would appreciate if you could shed some light


Thanks a lot!

1hz clock vhdl

you have to generate a counter div by 32....
on cpld data sheet you get the pin on which you have to connect the clk...
after ... ns is only for simulation not for synthesis...OK

pinout xc9536xl

An oscillator requires an amplifier with feedback and phase shift. In that schematic, U2A and its associated components provide that function. U2B and U2C square-up the waveform.

The CPLD doesn't provide a built-in oscillator/amplifier like you may find in a microcontroller. If you feel tempted to try it anyway, first read the last comment on this page:
**broken link removed**

Synthesis tools generally don't support VHDL's "wait" statement. You would need to implement a counter (very easy). If the oscillator runs at 32768 Hz, then a 15-bit counter would divide it down to 1 Hz. Beware that a 15-bit counter would consume a significant portion of the 36 macrocells in the tiny XC9536 CPLD.

maximum number of macrocells vhdl project

According to my rough estimation, the clock project most likely doesn't fit a XC9536 considering the 7-segment decoders, even without a frequency divider, when clocked at 1 Hz.

Regarding your oscillator circuit, you (or the original circuit designer) apparently mixed up two resistor values, it surely doesn't work as exactly drawn. Also, crystal manufacturers normally require an unbuffered inverter instead of U2A, but it hopefully works with HC00. Epson specifies R15 of 20 M, R14 of 500 k and C8/C9 of 10 p with LF watch crystal, an R14 of 470 ohms would be correct for MHz crystals.

P.S.: I forgot to mention, that a CD4060 counter contains a 2^14 divider and the oscillator circuit, I previously used it for LF clocks with watch crystals.

cd4060

Thanks a lot for all your responses.

If I eliminate the crystal option, I think at this point I have three choices:

-If I use an oscillator rather than a crystal (something like: https://uk.farnell.com/1278042/passives/product.us0?sku=EPSON-TOYOCOM-SG-3030JF ), would it be 'stable' enough? (With this I would still have to divide it inside the CPLD, which as you mentioned would take up lots of space?)

-If I divide the crystal using a 4060 to get 2hz, and then a 4013 to further divide by 2, it gives me a nice 1hz pulse, I've used this before when I built an all-logic binary clock. Again would this be stable enough? (No need to divide, nice and simple at the cost of two external components)

-As a last resort, I think I could just use a 555 to generate 1Hz (No need to divide, again addition of components)


If you were to make a choice which one would you go for, or is there a better alternative?


Your comments are much appreciated.

Cheers.

xc9536

A crystal oscillator should basically have the accuracy required for a clock. An error of e. g. 50 ppm would result in a deviation 4 sec/day, that's not very good, but should be acceptable. You can achieve higher accuracy by tuning a capacitor in the crystal circuit or use a more accurate oscillator.

The CD4060 suggestion was basically motivated by reducing part count. A single /2 divider should be better implemented in CPLD. On the other hand, you can build the complete clock from CMOS parts as many people did "in the last millenium".

cd4060 crystal oscillator

FvM said:

A crystal oscillator should basically have the accuracy required for a clock. An error of e. g. 50 ppm would result in a deviation 4 sec/day, that's not very good, but should be acceptable. You can achieve higher accuracy by tuning a capacitor in the crystal circuit or use a more accurate oscillator.

Click to expand...

That looks like the simplest option although do you reckon 36 macrocells will be enough for dividing it on top of all the other logic of the clock? One good thing is I am not using BCD or any other encoding, all the segments are directly connected to individual CPLD pins.

FvM said:

The CD4060 suggestion was basically motivated by reducing part count. A single /2 divider should be better implemented in CPLD. On the other hand, you can build the complete clock from CMOS parts as many people did "in the last millenium".

Click to expand...

The joys of CMOS eh? My previous clock project was a binary clock made out of 4060, 4013 4040, 4081, 4082 and some really old LEDs I found in the attic (to give that extra vintage look ) but this, If I can finish it, will be my first 'stand-alone' CPLD project (I've used the digilent spartan FPGA boards for lab assignments etc using VHDL) so I want to do 'all-that-can-be-done' in VHDL using the functions of the CPLD.


Thanks!

1 hz oscillator 555

I assume you are building a 4-digit HH:MM clock, and not a HH:MM:SS clock. Connecting 28 LED segments directly to the CPLD consumes 28 of the 36 available macrocells. (Or somewhat fewer if you don't need all the segments in the left digit.) You can use those segment registers as state-machine counters, but you'll still need six more macrocells to implement the divide-by-60 seconds counter. That doesn't leave enough macrocells to build a divide-by-32768 counter. I don't think there's any way to cram everything into a tiny XC9536.

A 555 could easily generate 1 Hz, or even 1/60 Hz, but the frequency accuracy would be too poor for a clock. A crystal oscillator is the way to go.

You might be able to buy a crystal oscillator with a built-in divider and 1 Hz output. I vaguely recall seeing one some years ago.

555 1hz clock

echo47 said:

I assume you are building a 4-digit HH:MM clock, and not a HH:MM:SS clock. Connecting 28 LED segments directly to the CPLD consumes 28 of the 36 available macrocells. (Or somewhat fewer if you don't need all the segments in the left digit.) You'll need six more macrocells to implement the divide-by-60 seconds counter. That doesn't leave enough macrocells to build a divide-by-32768 counter. I don't think there's any way to cram an entire clock project into a tiny XC9536.

Click to expand...

Ouch. I didn't even think of this. I was even thinking the CPLD might be an overkill for this project

Is there a formula on how to calculate how many macrocells my design would consume? All I know about macrocells is they consist of *some* flip/flops and an i/o cell so how would I go about 'estimating' how many macrocells my design would use? And for this simple clock would a XC9572 be enough?


Please excuse my questions as I said in the first post this is my first CPLD project and I would really like to get it up and working

Thanks!

32.768 khz circuit 1hz

A quick way to roughly estimate the required number of macrocells is to add up all the flip-flops in your design, plus any output pins that aren't directly tied to a flip-flop. Also, if your design contains large logic equations, some additional macrocells may be consumed. You can try building various designs in ISE to see what happens. I'm not a CPLD expert, so other folks may have better suggestions.

Using that estimation technique, you would need about 4*7=28 macrocells for the segment driver state registers, plus 6 macrocells for the divide-by-60 seconds counter, plus 15 macrocells for the divide-by-32768. That's about 49 macrocells. A scanned LED design would require a roughly similar number of macrocells. An XC9572 would be plenty big for either approach.

CPLDs are very small compared to an FPGA.

count seconds cpld

Synthesizing the design for the intended logic family is the only suitable approach to know the exact resource requirements, to my opinion. You may of course minimize the logic equations by hand and map it to CPLD macrocells. But apart from maximum number of logic terms for a macrocell, you also must consider particular routing constraints. This was necessary 20 year ago when designing GAL logic, without todays high-level tools.

If a seconds display is intended, multiplexing outputs may be necessary to fit a XC9572, I think.

crystal oscillator for cpld

I tried stuffing a simple multiplexed 4-digit 12-hour clock (28 flops plus 7 segment outputs) into an XC9536, and it fit pretty much as I expected. There was only enough room for about half of the input divider, so my input clock is 256 Hz. I get the feeling that the design is pretty tight, because I had to fiddle with the optimization settings to avoid running out of resources.

1hz 4060

I think I will go for an XC9572 just to be on the safe side and I will try to keep it as simple as possible using only 4 digits, 7 segments and I will also use a 4060 to get 2hz, which will reduce clock dividing in the CPLD.

I don't want to use multiplexing as I always seem to have problems with 'ghosting' :|


This thread has been of immense help, thank you all very much

cd4060 clock divider

Before selecting a CPLD, you can try implementing your design with ISE to see how well it fits.

To eliminate ghosting in a scanned display, briefly blank the display when stepping to the next digit.

Happy clocking!

xilinx flip flop 1 hz counter

You have to divide the clock (32.768KHz) by 2^15 to get 1Hz clock. It will solve your problem.