drifterz
Newbie level 5
Hi
I'm new to VHDL so please pardon my "silliness".
when I declare a signal (signal_a) as std_logic_vector and I wish to check for sign, is the statement below valid?
if (signal_a>=0) then
or should I specific the MSB explicitly:
if(MSB of signal_a ='0' )then
Thanks in advance.
I'm new to VHDL so please pardon my "silliness".
when I declare a signal (signal_a) as std_logic_vector and I wish to check for sign, is the statement below valid?
if (signal_a>=0) then
or should I specific the MSB explicitly:
if(MSB of signal_a ='0' )then
Thanks in advance.