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HI All help me please

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venkatesankalidass

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dear all ,
now currently work with ACTEL FPGA
for i am using ACTEL IDE tool

in this design i have one problem

while i simulate and synthesis
ERROR: Mismatch between the portlist of the corresponding symbol of the

please help me

i whant to finish the project as soons as possible

regards
venkatesan.k
 

I think you would need to create the symbol again.. Then try to simulate again.
 

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