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verilog equivalent of C code acc=acc+out;

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neefa

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verilog query

hi frz,
how to create a verilog code, for the equivalent C code
acc=acc+out;
Because of repeated addition of the output out, for each clock cycle we need that code.
 

verilog query

Assuming 'acc' is a register and 'out' is the input data (one word per clock cycle), building an accumulator is very simple:
Code: 
always @ (posedge clk)
  acc <= acc + out;
 

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