Synthesis Error in code to find power,and modulus...Help

I am using Xilinx to develop some code....The code finds power of two given no.s....Dont know where the mistake is...Finds some synthesis error.....

ERROR:Xst:528 - Multi-source in Unit <power> on signal <rsta>
Sources are:
Signal <rsta> in Unit <power> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <power> on signal <rstb>
Sources are:
Signal <rstb> in Unit <power> is assigned to VCC
CPU : 11.73 / 11.86 s | Elapsed : 11.00 / 11.00 s

IMP: The file is not a PDF it is a .v file..

Dont know how to find the power otherwise...help needed..

That's no synthesizable Verilog code. I think, the basic problem is a misunderstanding of Verilog operation principles. A common mistake is to apply concepts from procedural programming languages used with microprocessors.

When I understand right what you tried to achieve, you are regarding a module similar as a C function, with initial block executed on entrance of the function call. But it doesn't work that way. An initial block e. g. is executed only once during initialization of Verilog code, it can be used to initialize arrays or calculate constants. Actually, when synthesizing programmable logic, calculations in initial block are performed at compile time, resulting in a set of initialisation data for the logic cells. You probably wanted the initial block executed for each new set of input data, indicated by rst_xxx_in signal.

The point, where the compiler refuses to compile your code is the "Multi source" or multiple drivers issue. This is cause you are setting a reg signal from multiple places (two different always blocks). This is equivalent to two digital outputs driving the same input - it results in a short circuit. Within an always block, it would be allowed and the last assignment wins.

But aside from multi source issues, the code is missing an operational mechanismn to repeat the second always block when needed. You intended to achieve it by setting and resetting rstb, but that doesn't work. always@ (posedge rstb) would be synthesized as a group of synchronous Flip-Flops with rstb as a clock. You can't reset the clock input of a Flipflop from it's output. The rsta logic isn't synthesizable for similar reasons.

When coding a calculation scheme as the power algorithm, you have basically two options: You can try to realize it fully parallel, that means the result produced immediately. With power, it would imply a chain of 2^32 multipliers and additional multiplexers, obviously impossible.

Or you can perform the calculation serial. The rstb logic indicates, that you went this way. But then you need a clock to trigger the operation, one multiply at each clock cycle. The calculation would take somewhat long at maximum second_val, but it would be possible at least. So the solution is to have a clock signal for posedge and the rstx signals as enable signal in an if statement. The multi source issue could be solved by using only one always block.

As a general suggestion, you should analyze other Verilog code examples that perform serial calculations regarding their utilized control mechanism. There is e. g. a lot of serial multipliers and dividers (these function can also be peformed in parallel with bearable effort).

Hi deepavlsi,
Oh my, you've broken nearly every synthesis rule in the book!
In addition to FvM's suggestions, try this:

Here is ModelSim's display when calculating 7^9:

Thank You very much FvM and echo47...Thanks for your help...

Added after 2 minutes:

Please help me with the modulus code as well.....Once again,thanks for your effort guys...

Unlike power, modulus can be calculated faster than 2^n cycles as division remainder. It would need n cycles with a serial divider or "no" clock cycle using parallel divider core available for most FPGA, e. g. lpm_divide Megafunction with Quartus II.

But you can apply the very clear and straigthforward scheme, echo47 has demonstrated, also to modulus calculation.

There are ways to speed up the power calculation too.
For example, my code calculates 7^9 with eight multiplications: 7*7*7*7*7*7*7*7*7.
However, it could be done with only four multiplications:
temp = 7 * 7
temp = temp * temp
temp = temp * temp
result = temp * 7

Implementing that, and the modulus algorithm, I leave as exercises for the student.