Error: Node instance "u1" instantiates undefined

A little help please!

This is the section I've been having problems with:








LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;

ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSIC
PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;

SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);


BEGIN
CNT8 : PROCESS(clk,Counter)
BEGIN
IF Counter=138 THEN Counter <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN Counter <= Counter+1; END IF;
END PROCESS;


u1:MUSIC PORT MAP(address=>Counter , q=>ToneIndex, inclock=>clk);
END;


When Compiling, I was given this error:

Error: Node instance "u1" instantiates undefined entity "MUSIC"


But the componet "music " is right there! I'm really confused and donno where to start.

Re: A little help please!

Hi,

Where is the MUSIC architecture description ?

Yours,
Said.

A little help please!

I don't quite understand? "Music" is just a component? Only entity can be port mapped?

I've searched another example:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX2 is
port (SEL, A, B: in STD_LOGIC;
F : out STD_LOGIC);
end;

architecture STRUCTURE of MUX2 is

component INV
port (A: in STD_LOGIC;
F: out STD_LOGIC);
end component;

component AOI
port (A, B, C, D: in STD_LOGIC;
F : out STD_LOGIC);
end component;

signal SELB: STD_LOGIC;

begin
G1: INV port map (SEL, SELB);
G2: AOI port map (SEL, A, SELB, B, F);
end;

And this runns ok

A little help please!

Problems solved!

For some reason, I've deleted the file that defines the entity, but I forgot about it. Still, thanks for the help!