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sysnthesis report help...

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abhi_459

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after synthesis of any code...max combinational delay is calculated by iSE 6.2 vhdl.
in which gate delay is give.for the same device i have synthesized the code on ISE 6.1 and ISE 9.1.but the gate delay is differrent for the same device......can any one help me...whts the prob?????
 

Its not a very unexpected behavior.....

while migrating from one version to another ISE usually uses new internal
algorithms to optimize the logic inferred by synthesis.so its very common to get different results from different versions of ISE.(well provided that your design should have enough room for optimization i.e. if you have coded for a primitive designs such as FF, latch or mux then ISE should infer the same logic for a same device no matter what version it is..)

its not about just different versions there are may other factors affecting maximum delay calc.
such as routing , logic duplication,register balancing, effort level selected etc.
have you checked that you are using same options in both the versions.

regards
KeY
 

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