warning of output pins stuck at gnd or vcc (CPLD)

I often get annoying warning of output pins stuck at gnd or vcc. I know it means no harm, but is there any other coding method that I could get rid of them?

No, some pins are actually hardwired to VCC or GND. The warning wants to assure, that you didn't unintentionally forget to drive a pin. With most HDL tools, warnings can selectively be disabled.

I am using Quartus II. How can it be disabled?

To enable or disable specific HDL messages in your HDL, use the message_on and message_off synthesis directives. Both directives take a space-separated list of Message IDs. You can enable or disable messages with these synthesis directives immediately before Verilog HDL modules, VHDL entities, or VHDL architectures. You cannot enable or disable a message in the middle of an HDL construct.

A message enabled or disabled via a message_on or message_off synthesis directive overrides its HDL Message Level or any message_level synthesis directive. The message will remain disabled until the end of the source file or until its status is changed by another message_on or message_off directive.

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// altera message_off 10000
-- altera message_off 10000

FvM said:

// @ltera message_off 10000
-- @ltera message_off 10000

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thanks, but i think it doesnt work with Quartus II. keep getting error, instead of just warnings.

In my point of vue, if you get warnings about ouputs stuck at gnd or vcc, it might reflect the fact that your design generates always zero or one on the corresponding pins.
The warning is here to make you verify if you do not have any misconception in your design (vhdl or schematic), that conducts to this situation.

but i think it doesnt work with qu(at)rtus II. keep getting error, instead of just warnings.

Click to expand...

A unknown synthesis option shouldn't give an error, it's just a comment. I suggest, that you read the quoted instructions in Quartus II manual yourself and use the suitable synthesis options. I posted Verilog and VHDL version together, assuming you would use what fits your design. Also the 10000 has to be replaced with the warning number that you want to suppress.

However, I'm not absolutely sure, if "pin stuck to xx" warnings can be disabled this way, but I assume, that this works when the said synthesis option is placed in the top design file. Alternatively, warnings can be disabled in the Quartus GUI, the method is explained in the same Quartus manual chapter.

Added after 19 minutes:

It turns out, that the "stuck pin" warning can't be supressed, cause the ID 13401 isn't in the range of regular synthesis warning IDs, although the warning is issued during Analysis & Synthesis phase. So apparently, the warnings can't be suppressed. Strange indeed.

ooh...

thanks for the information =)

Added after 12 minutes:

robinh said:

In my point of vue, if you get warnings about ouputs stuck at gnd or vcc, it might reflect the fact that your design generates always zero or one on the corresponding pins.
The warning is here to make you verify if you do not have any misconception in your design (vhdl or schematic), that conducts to this situation.

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yup. that's the case =)
just those warning are quite annoying.

probably there is another method of coding that would omit such warning? :|
i'm using something like 11100000 WHEN '0' ELSE 10101111... hmmm..

McMurry said:

I often get annoying warning of output pins stuck at gnd or vcc.
I know it means no harm, but is there any other coding method that I could get rid of them?

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I think you are wrong;
it usually means you did something wrong if your
output stuck vcc/gnd;
I'd never try to filter out such warnings;

J.A

it usually means you did something wrong if your output stuck vcc/gnd

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Not necssary. In some cases, you have e. g. a chip enable, that is permantly active in a design. Then you get the warning. With Quartus, there are exactly two warnings for outputs:

1. A synthesis tool warning, when an output is set to a constant level from HDL code. The discussed "11100000" WHEN '0' ELSE "10101111" would e. g. issue this warning for several bits.

2. A fitter warning issued for any defined output pin, that has a constant level either set in HDL code or by default cause the pin isn't driven at all.

I generally agree, that the warning has the important purpose to reveal inactive resources in the design, together with other warnings for registers without clock or inputs not driving logic, it can help to find design errors.

FvM said:

Not necssary/.../

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right, that's why I said 'usually', not 'always' ;
how many times fpga pins are used to drive stable logic level 1/0 - 1% ?
these devices are slightly too expensive to use them as a connection
to gnd or vcc ;
so my advice - never filter out this warnig because you can mask out
a hint of a serious error in your rtl code;
J.A