Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

CLOCK MULTIPLIER AND DIVIDER

Status
Not open for further replies.
S

suru

Full Member level 3
Joined
Aug 31, 2007
Messages
157
Helped
4
Reputation
14
Reaction score
1
Trophy points
1,298
Activity points
1,934
clock multiplier vhdl

HOW TO GET CLOCK FOR THE FOLLOWING EXPRESSIONS

CLK1= 4 TIMES OF CLK( MASTER CLOCK)


AND CLK2= 1/4 TIMES OF MASTER CLOCK
 

clock multiplier vhdl

for 1/4 times of master clock, flop the clock twice i.e.(q2 <= q1), (q1<=clk) , should work.
 

dcm multiplier divider

If you can live with the added jitter you can always try the built in clocking functions/capabilities of the device you are using..i.e. DCM in a Xilinx part.

E
 

dcm clock multiplier

for the clock of 1/4 of the original frequency, just make a clock divider....a circuit that counts every 4 clock cycles of the original clock and generates 1 pulse of clock...

for the multiplication, there is no way to design a clock multiplier in VHDL....so you'll have to use a PLL or a DCM (Digital Clock Manager)...depending on your board...
 

use PLL, because output of PLL is connected to the global clock routing. When using counter for the clock dividing output in most FPGA is not connected to clock routing, in this case seting up timing constrains become unpredictable
 

In a modern Xilinx FPGA, you can connect a counter's output signal to a low-skew global clock net by simply inserting a clock buffer primitive such as BUFG. You won't have much control over the buffer's propagation delay, but that's fine for some applications.
 

sree205 said:
for 1/4 times of master clock, flop the clock twice i.e.(q2 <= q1), (q1<=clk)
Click to expand...
I guess, it will add a shift\delay rather than dividing...
 

yes, u r right, my fault
 

Use frequency divier to divide the frequency by 4 and a PLL to multiply by 4 you CLK.
 

this will definitely work, although implementing this is kinda a risk coz of glitches.

module clk4(clk,reset,div2,div4);

input clk,reset;
output div2,div4;

reg div2,div4;

always@(posedge clk or negedge reset)
if(!reset)
div2<=1'b1;
else
div2 <= ~div2;

always@(posedge div2 or negedge reset)
if(!reset)
div4 <= 1'b1;
else
div4 <= ~div4;

endmodule
 

The simplest solution is to just use the DCM or PLL built into your FPGA.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top