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How to pass the values in Verilog during run time?

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balan

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hi guys,

how to pass the values in verilog during run time. by generic statement it can be done in VHDL. how to do it in verilog.



thank you,
 

verilog

using Parameter , if i do not mistake .
 

Re: verilog

hi,
Thank you,
 

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