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why more clock skew when use DCM rather than no DCM?

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Hi, all
there are several clock in my design, here is two case for comparison:
1, Input only one clock,'clk_in', and all other clocks are derived from this input clock by DCMs, specify only the input clock period, the design report HOLD time violation.
2, Input all clocks from external , and no DCM is used, specify the all the input clock period respectively, and the result reports no timing violations.
After compared the timing reports of the two cases, I found the clock skew in the first case is much bigger then the second case, what's the problem? how should I set the constraints in the first case?

Thanks
 

I would suggest looking at the two designs to see what kind of clock resources were assigned to each. It is possible that Case #2 is using a global clock buffer and Case #1 is using a local clock buffer.

Until you get the DCM output on a low skew clock line using a global clock buffer, you will see clock skew. When using a DCM, I have had to explictly instantiate the global clock buffer. You can do this in HDL by calling out the Xilinx primative.

---- Steve

P.S. Open the designs with FPGA Editor and highlight the clock routing. Global clock lines with low skew are routed through the center of the chip.
 

thanks for you answer.
I do buffered the DCM output clock by primitive 'BUFG'. I'll take a look at the FPGA editor tomorrow.
 

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