dilan2005
Member level 4
hi
i need to interface BLOCK ram (in spartan3E) with MII ethenet interface . as it seems to me the both ram and eth are operatord on positve clk edge . i obtain the clk from ethernet chip to drive the entire logic. it is obvious as i think data is not ready when MII reading from the data lines.
please show me the way. i really appreciate if the solution in verilog.
Thanks
dilan
i need to interface BLOCK ram (in spartan3E) with MII ethenet interface . as it seems to me the both ram and eth are operatord on positve clk edge . i obtain the clk from ethernet chip to drive the entire logic. it is obvious as i think data is not ready when MII reading from the data lines.
please show me the way. i really appreciate if the solution in verilog.
Thanks
dilan