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Problem with a code for assigning RAM location

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anandanips

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the following modules is required 255 ram locations of 8 bit wide.i am writing code like this.
module xy(x,y,ram);
input x,y;
output [7:0] ram[0:255];

reg[7:0] ram[0:255];


to assigning value of ram location i am writing like
ram[0]=data;
ram[1]=data;
ram[2]=data;
ram[3]=data;
ram[4]=data;
.
.
.
.
.
.// where data is 8 bit wide.
that statements are exeuting in different case .
for output only one assignment statement (as above) will be appear.
my proplem is ,i am getting 2 error in the place of array declattion:
output [7:0] ram[0:255];
reg[7:0] ram[0:255];
so , please can anyone clear my mistakes.and say the above assignment is correct or not also
 

answer to me

try this

module ram_data(
output wire [7:0] data,
input wire [17:0]address,
input wire ce,
input wire oe,
input wire we
);


reg [7:0] mem[255 : 1];

assign data = ce?(oe ?( we? 10'bz : mem[address]) :10'bz): 10'bz ;

initial
begin

mem[1] = 8'b01000000 ;// 64
mem[2] = 8'b00111111 ;// 63
mem[3] = 8'b00111100 ;// 60
mem[4] = 8'b00111000 ;// 56
mem[5] = 8'b00110001 ;// 49
mem[6] = 8'b00101010 ;// 42
mem[7] = 8'b00100001 ;// 33
mem[8] = 8'b00010111 ;// 23
mem[9] = 8'b00001100 ;// 12
mem[10] = 8'b00000010 ;// 2
.
.
.
.
end

endmodule
 

answer to me

Verilog doesn't allow passing a register array (such as 'ram') through a module port. Try passing only the 8-bit address and 8-bit data signals, as kalyansrinivas described.

It may help the discussion if you could show the complete module rather than just a few lines of code.

Please ask follow-up questions in the same discussion, instead of creating a new discussion:
 

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