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Delay issue-----urgent

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deeptijohar

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How will delay is generatedin verilog. What is circuit for edge triggerred and level trigerred inpus.
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edge triggered f-flop

level triggerd latch

dealy can be generated by a counter
 

to generate delay there is a cmd 'wait'.
But use this only for simulation purpose.
While synthesis generate counter circuit.
 

Delays are generated via counter

If u want to perform a certain task afer a certain time just calulate the time in terms of counter value
and then trigger ur task at that particular counter value
 

sandhya.im said:
to generate delay there is a cmd 'wait'.
But use this only for simulation purpose.
While synthesis generate counter circuit.
Click to expand...

Even for Simulation,you can't declare in process with sensitivity list
 

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