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usually generate statement is used for synthesis purpose....
but its very vague to say generate statement that is sythesizable...
because its not the generate statement that is sythesizable....
what you write under generate that makes it synthesizable or not..
if you write synthesizable constructs under generate then its synthesizable else not...
what about the inital and timing (#) statements is it like generate function or else.is it true for inital statement?.what we are writing inside the inital block will decide,it's synthsizable or not.why the tool will operate differently for different statement? plz help me...thanks in advance....
inital and timing (#) are verilog constructs....
after, wait etc in vhdl and '#' in verilog or any timing control releted statements are not synthesizabe ...no matter it is in verilog or vhdl. .
they are not like generate statement ....
no matter what ever you write under it, initial statement is NOT synthesizable..
initial are very useful construct while writing testbenches.
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