Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why latches are inferred because of the incomplete if else statement in Verilog?

Status
Not open for further replies.

reninroy

Junior Member level 1
Joined
Feb 26, 2008
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,389
why latches are inferred because of the incomplete if else statement..?
thanks in advance....
 

Re: verilog

unless you don't specify all the cases it is assumed (by synthesis tool) that you don't want to change the output values for cases other than the specified ones.Hence the values would be latched....thats why it (synthesis tool )infers latches
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top