vandelay
Advanced Member level 4
Hello.
I am not too experienced with FPGA, but in a new project I feel there are no way around. I use a Blackfin DSP (ADSP-BF533) running at 500MHz, and need to equip it with hardware acceleration for geometry functions (CORDIC).
My thoughts are wiring up the FPGA (a Xilinx Spartan-3, XC3S1000) on the Blackfin data/address bus, where an SDRAM device already resides. I am thinking writing the geometry parameters to the FPGA as if it was SDRAM (above actual SDRAM addressing), then reading results back as if it was SDRAM (after a short delay possibly).
Any comments on this approach? is it a good idea, a bad idea?
Have anyone done something along these lines with an FPGA?
I do have a 16-bit wide PPI bus (Parallel Peripheral Interface) that I could use for interfacing to the FPGA, but I think this might be faster and cleaner if I can make it work.
Any comments are welcome!
I am not too experienced with FPGA, but in a new project I feel there are no way around. I use a Blackfin DSP (ADSP-BF533) running at 500MHz, and need to equip it with hardware acceleration for geometry functions (CORDIC).
My thoughts are wiring up the FPGA (a Xilinx Spartan-3, XC3S1000) on the Blackfin data/address bus, where an SDRAM device already resides. I am thinking writing the geometry parameters to the FPGA as if it was SDRAM (above actual SDRAM addressing), then reading results back as if it was SDRAM (after a short delay possibly).
Any comments on this approach? is it a good idea, a bad idea?
Have anyone done something along these lines with an FPGA?
I do have a 16-bit wide PPI bus (Parallel Peripheral Interface) that I could use for interfacing to the FPGA, but I think this might be faster and cleaner if I can make it work.
Any comments are welcome!