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Regarding dualport RAM

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kavitha_bonthu

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Hello every body
I want to program external Synchronous dualport Ram through FPGA(xilinx)
We have tied thye CE(active low) to always low.
All other signal s are programmed correctly,still out put is not coming.
is it must to toggle CE.
We are using Cyprus Synchronous dualport Ram(512kx18).
 

you need to elaborate : what is "output not coming", what exactly is the ram you are using, and how you connect to it.
 

Hi,

If you can still explain the status of other control signals like, WEN, REN, WCLK, RDCLK, etc.. then I can try to help you.

Regards,

N. Muralidhara

CRL-BEL
 

I think problem is not with ce as i have interfaced a sram chip to fpga where the data sheet shows ce toggling and i have kept it low and still i was able to read and write data
 

Hello kalyan srinivas
Thanks for your info ....
Which SRAM you are using
is it possible to send your HDL code
 

hi,
can you provide more information about the dual port sram?

are you using the block ram from the coregen?

you could check all the control signal like ce, ren,wen...etc.... check the control signal are low enable or high enable.
 

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