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The reason and solution for XST ERROR 1534

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BlackOps

BlackOps

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Hello,

My VHDL code for Horizontal counter seems to compile without errors, however during the synthesizing process in ISE, it gives me the following error:

ERROR:Xst:1534 - Sequential logic for node <value> appears to be controlled by multiple clocks.

what is the reason? whats wrong with value?

here is the code:
Code: 
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to add STD_LOGIC_VECTORs

ENTITY HCount IS PORT (
Clock:         IN STD_LOGIC;
Clear:         IN STD_LOGIC;
Rollover:      OUT STD_LOGIC;
H_cntD:        OUT STD_LOGIC;
H_cntDE:       OUT STD_LOGIC;
H_cntDEB:      OUT STD_LOGIC;
H_cntDEBC:     OUT STD_LOGIC);

END HCount;


ARCHITECTURE Behavioral OF HCount IS

	CONSTANT B: INTEGER :=  95;
	CONSTANT C: INTEGER :=  45;
	CONSTANT D: INTEGER := 640;	
	CONSTANT E: INTEGER :=  20;

SIGNAL value: STD_LOGIC_VECTOR(9 DOWNTO 0);

BEGIN



PROCESS (Clock, Clear)  
BEGIN

IF Clear = '1' THEN
value <= (OTHERS => '0'); 
ELSIF (Clock'EVENT AND Clock='1') THEN
value <= value + 1;
END IF;

        IF (value =  D) THEN       -- TEST FOR 640
            H_cntD <= '1';
            ELSIF 
            (value =  D+E) THEN      -- TEST FOR 660
            H_cntDE <= '1';
            ELSIF
            (value =  D+E+B) THEN      -- TEST FOR 755
            H_cntDEB <= '1';
            ELSIF
            (value =  D+E+B+C) THEN      -- TEST FOR 800
            H_cntDEBC <= '1'; Rollover <= '1'; value <= (OTHERS => '0'); 
        END IF;
        

END PROCESS;


END Behavioral;

thanks
 

xst:1534

You are asking ISE to create both a register output (first part of process) and a latch output (second part of process) for the same signal.

The first part is a register pattern because of clock event.

The second part is a latch pattern because it is not part of the register pattern, and also because the output (looks like a destination) signal is not specified for every case. Specifying the state of value for every case in this part will not cure the problem, as it will produce "combinational feedback" - which is bad if it does not form a latch.
 

xst 1534

well, totally remaked this code.

now i dont get exactly this warning. but i get the following ones:

WARNING:Xst:1989 - Unit <VGActrl>: instances <R[0].RED_OUT>, <R[1].RED_OUT> of unit <AND_3> are equivalent, second instance is removed

WARNING:Xst:1290 - Hierarchical block <SRFlipFlop2> is unconnected in block <VGActrl>.
It will be removed from the design.


INFO:Xst:2261 - The FF/Latch <GREEN_REGISTER/q_7> in Unit <VGActrl> is equivalent to the following 15 FFs/Latches, which will be removed : <GREEN_REGISTER/q_6> <GREEN_REGISTER/q_5> <GREEN_REGISTER/q_4> <GREEN_REGISTER/q_3> <GREEN_REGISTER/q_2> <GREEN_REGISTER/q_1> <GREEN_REGISTER/q_0> <RED_REGISTER/q_7> <RED_REGISTER/q_6> <RED_REGISTER/q_5> <RED_REGISTER/q_4> <RED_REGISTER/q_3> <RED_REGISTER/q_2> <RED_REGISTER/q_1> <RED_REGISTER/q_0>
INFO:Xst:2261 - The FF/Latch <BLUE_REGISTER/q_7> in Unit <VGActrl> is equivalent to the following 7 FFs/Latches, which will be removed : <BLUE_REGISTER/q_6> <BLUE_REGISTER/q_5> <BLUE_REGISTER/q_4> <BLUE_REGISTER/q_3> <BLUE_REGISTER/q_2> <BLUE_REGISTER/q_1> <BLUE_REGISTER/q_0>
INFO:Xst:2261 - The FF/Latch <SRFlipFlop4/Q> in Unit <VGActrl> is equivalent to the following 2 FFs/Latches, which will be removed : <SRFlipFlop2/Q> <SRFlipFlop1/Q>
WARNING:Xst:1710 - FF/Latch <BLUE_REGISTER/q_7> (without init value) has a constant value of 0 in block <VGActrl>.
WARNING:Xst:1710 - FF/Latch <GREEN_REGISTER/q_7> (without init value) has a constant value of 0 in block <VGActrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SRFlipFlop4/Q> (without init value) has a constant value of 0 in block <VGActrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <HSYNC_REG/q> (without init value) has a constant value of 0 in block <VGActrl>.
WARNING:Xst:2677 - Node <HCOUNTER/Rollover> of sequential type is unconnected in block <VGActrl>.


i did include this in my top.vhd file

library unisim;
use unisim.vcomponents.all;

could this library cause these warnings? some ppl say that i must include virtex2 pro library for synthesizing... but some say that when i choose project and set up Virtex2 Pro chip... i dont have to include it... so i dont know what to do..

could you say me which library i must include for successfull synthes process for Virtex 2 pro chip?

please take in notice that the syntax check process was without errors of cuz.

thanks
 

xst: 1290 - hierarchical

You need to look at the **broken link removed**.

library unisim;
use unisim.vcomponents.all;
Click to expand...

You need this only if you use any of the primitive design elements listed in the Libraries Guide. If you use only behavioral code, the unisim library is not needed.

I think you need to rethink your logic. Think in terms of "total" functions. You want to set some signals when some equality is true. But what do you want to set these signals to when the equality is false?
 

warning:xst:1290 -

well, i changed the code, now i think it is ok:

Code: 
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to add STD_LOGIC_VECTORs

ENTITY HCount IS PORT (
Clock:    IN STD_LOGIC;
Clear:         IN STD_LOGIC;
Rollover:      OUT STD_LOGIC;
H_cntD:        OUT STD_LOGIC;
H_cntDE:       OUT STD_LOGIC;
H_cntDEB:      OUT STD_LOGIC;
H_cntDEBC:     OUT STD_LOGIC);

END HCount;


ARCHITECTURE Behavioral OF HCount IS

	CONSTANT B: INTEGER :=  95;
	CONSTANT C: INTEGER :=  45;
	CONSTANT D: INTEGER := 640;	
	CONSTANT E: INTEGER :=  20;

SIGNAL count: STD_LOGIC_VECTOR(9 DOWNTO 0);



BEGIN
	Horizontal_Counter: PROCESS(Clock,Clear)
	BEGIN
		IF (Clear = '1') THEN
			count <= (OTHERS => '0');

		ELSIF (Clock'EVENT AND Clock = '1') THEN

			IF (count = B+C+D+E) THEN
			   H_cntDEBC <= '1';
				count <= (OTHERS => '0');
				Rollover <= '1';	-- generate clock for vertical counter
			ELSE
				count <= count + 1;
				Rollover <= '0';
			END IF;


			IF (count = D+E+B) THEN

				H_cntDEB <= '1';
			ELSIF (count = D+E) THEN
				H_cntDE <= '1';
			ELSIF (count = D) THEN
				H_cntD <= '1';
			END IF;


		END IF;
	END PROCESS;


END Behavioral;

i get less warnings now... but i stil get warning that it wants to unconnect my HCOUNT... why?

code looks good to me, and syntax check is good also... why does it want to unconnect everything?


here is a fragment of code from my top.vhd file:

Code: 
			R: FOR n IN 0 TO 7 GENERATE
			RED_OUT:		AND_3
			PORT MAP ( I0		=>		h_data_on,
						  I1		=>		v_data_on,
						  I2		=>		'1',
						  O		=>		r_out(n));
						  END GENERATE;
						  
			RED_REGISTER:	dffn
			GENERIC MAP(8)
			PORT MAP (	Clock		=>		Clk,
							reset		=>		Res,
							ckena		=>		'1',
							d			=>		r_out,
							q			=>		r_outf);

here i create 8 AND elements each with three inputs... and then register them with 8 bit wide D flip flop..

what else could be wrong?
 

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