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active low reset or active high reset

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dinesh.4126

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deassertion reset

Hi,
Interview Quest:In a sync. reset Design if duration of each clock width is of 50ns.and if reset is asserted at 10 ns and de-assert at 20ns and again assert at 40ns.then what is O/P.?

thanx,
Dinesh
 

Assert or Deassert Reset

What do you mean with O/P?

Added after 5 minutes:

The output should be logic 0.
 

Re: Assert or Deassert Reset

Hi,
Interviewer asked me that supposed in our design clock width is of 50ns.and if reset is asserted at 10 ns and de-assert at 20ns and again assert at 40ns.then what will be the effect on O/P.
 

Re: Assert or Deassert Reset

Hi,

Still you are not telling about the output of what you are looking for.

Regards,

N. Muralidhara

CRL-BEL
 

Re: Assert or Deassert Reset

I guess the output will be '0' logic. Since it is a syn reset, the reset condition is always detected....
 

Re: Assert or Deassert Reset

Hi,
We are defining duration of each clock pulse is of 50ns and Pos edge event is happening and reset is asserted at 10 ns and de-assert at 20ns and again assert at 40ns.then what will be the effect on O/P.
so in a synch. Design if we are talking clk'event then what i am thinking is that is reset will be detected at 10 ns,20 ns ,40 ns etc.Because we are talking Pos edge event and reset we are giving in B/W of clock pulse at 10 ns,20 ns etc.
Am I right or wrong??
 

Assert or Deassert Reset

Do you mean this?
 
Re: Assert or Deassert Reset

it is like this.....
 

Assert or Deassert Reset

Well, in this case the output will stay at 0.

Added after 52 minutes:

If reset remains 1 after the 40th ns, then the output will become 0 at next positive transition (edge) of the clock input.
 

Assert or Deassert Reset

The question itself is very vague as the starting point of the signal is not being mentioned wrt to the clock.

That is most probably what the interviewer wanted to check more in concept of synch. circuit instead of the answer.
 

Assert or Deassert Reset

dinesh.4126 said:
it is like this.....
Click to expand...

i'm just curious about this question, it had mention that the clock is 50ns high and 50ns low, and the reset is sync reset.

so assume the "50ns" was the system clock and +ve edge, the reset pulse length should at least 100ns so the signal can be insync with the 100ns clock domain.

assume the sync reset is generate from another faster clock domian, my opinion will be the signal consider out of sync and the 10ns-20ns pulse should be ignore since it is not align with the +ve clock edge so no valid reset condition.

if the reset signal high after 40ns-infinity, and the sync reset is valid and the system will go in reset. state.

PS i assume the reset signal is active high.

if it's a async reset,than yes, the 10-20ns reset pulse will give the system a valid reset.

correct me if i'm wrong.
 

Re: Assert or Deassert Reset

Yes, in this design with respect to 50ns ON-time clk, the reset condition is never alligned to the +ve or -ve edge of clk. The time when FF gets triggered, the reset condition will be unnoticed. In order to achieve a proper reset cond, it should be greater than 100ns..In this question, the system will be in reset condition only...It's like this..
1) At 0ns, the reset cond willbe checked for..Now reset = '0'
2) At 10ns, the reset occurs. But it's not detected
3) At 20ns, the reset de-asserts,again it's not detected
4) At 40ns,the reset asserts again for ever. It's again not detected
5) At 100ns, the reset is being detected and the system willbe on Reset now and forever
 

Re: Assert or Deassert Reset

i agree with vsmguy : this kind of question is to filter which one really has experience with design then one that has not.

what he actually expect from you is to clarify, or developp the issue further more, thus you generate an interaction, which is most importent in work.
 

Assert or Deassert Reset

@shawndaking : My point exactly !

Do you hire guys directly ? I mean are you an empaneled interviewer ?
 

Re: Assert or Deassert Reset

My personnel opinion or what I'd ve replied to this as a solution would be the answer that I said in my last post and then would've stated "Any possible active high reset which has a timming of anything below to the clk period cannot be detected and have it's own chance of missing,so such designs aren't encouraged"...The interviewer might've expected a better solution what this design might give as a result in hardware and how far good this is?. One should understand that he wasn't pretty expecting the very output of this design,but was expecting the explanation how u've understood the design.
 

Assert or Deassert Reset

@xtcx : No dear :)

Asynchronous inputs have nothign to do with the clock.

Even if they did, they don't have anything much realiable for edge triggered clocks.

Why ?

Any asych signal ovverides the clock.

Secondly, the behaviour of a sync circuit towards pulses smaller than the clock width is undefined - it's not that they do not effect the circuit.

Hint - consider the case when the "short pulse" meetes the setup and hold time requirements and enough to last one edge/the active edge of the clock.

As usual.. I would be glad to stand corrected !
 

Re: Assert or Deassert Reset

No matter if the reset is sync or asynch with the system clock, a good reset must be stable a few clock cycles, and probably that want to heard the interviewer...
 

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