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How to fix multi source errors in Verilog code?

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andrew257

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hi all,

i keep getting an error message when i try to compile my verilog code.

it refers to a multi source. Now i can see where the error is occuring but i dont know how to fix it.

basically i have the outputs of 3 modules all connecting to the same input on another module.

e.g

output1 ----------|
output2 ----------|-----------input1
output3 ----------|

is there away around this?

thanks
 

Re: multi source errors

A way around would be to consider what you try to achieve. The shown structure is logical impossible. As moving in three directions simultanously.
 

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