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ya but that DCM primitive is giving me problems during sysnthesis(some time variables are used inside the primitive apparently) If u make it work please tell how u did that
Hi mindstream, which method are you using to put the DCM into your project? What exactly does the error message say?
If you are directly instantiating the primitive into your HDL, then here's a Verilog example that uses two DCMs. It may be more complex than what you need, but see if it compiles for you, or if you still get synthesis errors:
#968496
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