parallel to serial converter

jigisha sureja

i need to implement a parallel to serial converter,and i implemented it.
the code is below:
module partoser(par_data,clk,data_rdy,ser_out);
input clk,data_rdy;
input [7:0]par_data;
output ser_out;
reg [7:0]par1;
always@(posedge clk)
begin
if(data_rdy)
par1 <= par_data;
else
if(!data_rdy)
par1[1:0]<= par1[2:1];
par1[2:1]<= par1[3:2];
par1[3:2]<= par1[4:3];
par1[4:3]<= par1[5:4];
par1[5:4]<= par1[6:5];
par1[6:5]<= par1[7:6];
end
assign ser_out = par1[0];
endmodule

For the simulation output it is taking only the zerth position bit as the serial output.
my doubt is if we r sending an 8 bit no means,whether the method of parallel 2 serial is correct if we get only the zeroth position bit.iam attaching my output here.

Chech and study the RS232 port here
https://www.fpga4fun.com/SerialInterface4.html

The simulation behaves as expected, no shift operation for data_rdy==1. The code is basically correct, but could be reduced to
par1[6:0]<= par1[7:1];
Optionally, you may want to shift in a defined value of 1'b0 or 1'b1;

P.S.:I didn't understand, that this should be a RS232 transmitter, which would need an additional start bit and framing logic.

hi.......
there are many books that u can check for this.some of good books are
perry,zuroski.i know in zorouski the prog is given.i dont know the perfect spelling for this book,but its pronounsiation is like that.i will reply if i will get the name of this book 4m my library.plz mail me for reminder at

j_sureja@yahoo.co.in

i will find it for u with page numbers.....
best luck

thx sureja.
hai FvM, i didnt get ur point.hw can we reduce to
par1[6:0]<= par1[7:1];
plz modify in the code.

it replaces 6 lines in your code with identical result

par1[6:0]<= par1[7:1];
instead of
par1[1:0]<= par1[2:1];
par1[2:1]<= par1[3:2];
par1[3:2]<= par1[4:3];
par1[4:3]<= par1[5:4];
par1[5:4]<= par1[6:5];
par1[6:5]<= par1[7:6];

You are not loosing any bit as you are shifting all the bit outputs.
Care has to be taken as to see that the shifting is done exactly for eight bits and the ready signal comes every 8th clock cycle.

If the ready doesnot arrive for a long long time, you may be shifting out all zeros or all ones based on what you were shifting in at the MSB location. You may let the external world know when the shifted out data is valid. The external world can also use the ready signal, however that will complicate the matters for it.