Verilog Module instantiation in VHDL

verilog instantiation

Hi all
I am a verilog user , I am facing problems in instantaiting verilog module into VHDL
Below is the instantiation which i did

CPU: Calc PORT MAP(
eof => eof,
blank => blank,
clk1x => clk,
r => r,
rmd => rmd,
mlpl => mlpl,
sqr => sqr,
quo => quo
);
But the compiler is giving syntax error
Undefined symbol 'Calc'.
Where as Calc.v is the verilog file which i am trying to instantiate

can any body help me how to correct this error

instantiation in verilog

i think you forgot component declaration for calc

verilog module instantiation

COMPONENT Calc
PORT(
eof : IN std_logic;
blank : IN std_logic;
clk1x : IN std_logic;
r : IN std_logic_vector(2 downto 0);
rmd : OUT std_logic_vector(7 downto 0);
mlpl : OUT std_logic_vector(31 downto 0);
sqr : OUT std_logic_vector(31 downto 0);
quo : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;

CPU: Calc PORT MAP(
eof => eof,
blank => blank,
clk1x => clk,
r => r,
rmd => rmd,
mlpl => mlpl,
sqr => sqr,
quo => quo
);

But if i go for components (as done above)
I get this much of errors


ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 489. parse error, unexpected COMPONENT
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 492. parse error, unexpected IN
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 493. parse error, unexpected IN
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 494. parse error, unexpected IN
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 495. parse error, unexpected TOKOUT
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 496. parse error, unexpected TOKOUT
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 497. parse error, unexpected TOKOUT
ERROR:HDLParsers:164 - "F:/XESS/Programms/trial/Video Modification For corelation/video.vhd" Line 498. parse error, unexpected TOKOUT

instantiate verilog module in vhdl

have you defined the entity and architecture correctly & after component and signal declaration you have to start with begin for logic description

instantiate verilog in vhdl

Thnx for ur help
But i know very less about Vhdl

I am attaching both files (Problem >xs3_video> calc.v & video modified.vhd)
can you plz instantiate it for me
Plz

module instantiation in verilog

i Have seen the code mistake is that component declaration should be above begin just cut the component part and paste it above begin