How fast is our FPGA chip running?,how to check out?

errorar:228

For my FPGA(Spartan 3,speed grade -4) I have set the system clock speed of 100MHz.I never noticed any difference in my performance yet,but recently I noticed that at the end of the synthesis process,the ISE gives a tabulation which displays(approximately)

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 24.976ns (Maximum Frequency: 40.038MHz)
Minimum input arrival time before clock: 9.585ns
Maximum output required time after clock: 7.484ns
Maximum combinational path delay: No path found something like that!. I think this is displayed at the last of synthesis.

I don't understand this!, the ISE still didn't complete implementation(routing,placing,etc) but how could it just report my maximum clk input is limited to some value?...Also this maximum clk speed limitation varies with different design!...Please clarify me why xilinx have stated 320MHz for spartan 3 chip clk speed,but why the synthesis process reports like this?.Is this due to the FF latency when cascading or due to the speed grade?....Thank you fellas!.

fpga chip

The XST synthesizer compiles your HDL and then makes a quick estimate of how fast your design will run before it beings place and route. If the estimate is much worse than your timing constraints, it aborts without running place and route.

That 320 MHz value sounds like some ideal situation. Most Spartan-3 designs won't go that fast. Your max speed depends mostly on how much combinatorial logic you put between flip-flops, the route length, and the fanout.

chipp running

Alright, but without making any placing and routing action, how could the synthesis step decide my maximum clock speed?....Also when I want to run my design with 80MHz,the system only gives 24MHz and hell with it, how can I make my design morre time-specific?...So without taking a look at this will completly riun our design if it's purely time-based?....What is the solution to obtain maximum clock rating for our design?....Do you have any idea for this?....

any way to check speed grade of fpga?

XST can somehow estimate the ideal timing even before routing. It knows the speed of the flops and gates and other devices, but not yet the actual routing delays.

Oops, wait, the early abort may occur at the beginning of place and route, instead of at the end of XST synthesis. I forget exactly. Can you show a snippet of the actual error report? A common error message is "ERRORar:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary follows . . ."

You can examine the timing error report to see which signal is causing the timing violation, and try to understand why it occurred. For most projects, the best way to increase max clock speed it to use pipelining.