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Help me out with signal assignment in VHDL

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BlackOps

BlackOps

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Please could you look now at this signal assignment.. i know that bit vector assignment must be with '<=' but, now i am doing signal assignment in the structural top VHDL code..

here is the code:

Code: 
    -- Horizontal counter interconnection    
        HCOUNTER: HCount
        PORT MAP ( Clk          =>   Clock;
                   Res          =>   Clear;
                   H_cntD       =>   hd;
                   H_cntDE      =>   he;
                   H_cntDEB     =>   hb;
                   H_cntDEBC    =>   hc;
                   Rollover     =>   RollClk; -- Output goes to VCount clock
                   Q            =>   Col_OUT );

here are errors:
Code: 
Top.vhd(81): near ";": expecting: ')' ','
Top.vhd(83): near "=>": expecting: <= :=
Top.vhd(84): near "=>": expecting: <= :=
Top.vhd(85): near "=>": expecting: <= :=
Top.vhd(86): near "=>": expecting: <= :=
Top.vhd(87): near "=>": expecting: <= :=
Top.vhd(88): near "=>": expecting: <= :=

Clk,Res, hd,he, hb, hc, RollClk and Col_OUT are SIGNALS

Clock,Clear - are inputs to the HCount element
Rollover,Q,H_cntD,H_cntDE,H_cntDEB,H_cntDEBC - are Outputs of the HCount element
 

vcom-1136

BlackOps said:
Code: 
    -- Horizontal counter interconnection    
        HCOUNTER: HCount
        PORT MAP ( Clk          =>   Clock;
                   Res          =>   Clear;
                   H_cntD       =>   hd;
                   H_cntDE      =>   he;
                   H_cntDEB     =>   hb;
                   H_cntDEBC    =>   hc;
                   Rollover     =>   RollClk;   -- Output goes to VCount clock
                   Q            =>   Col_OUT );

Well this is not a correct way to instantiate a component

try

Code: 
  -- Horizontal counter interconnection    
        HCOUNTER: HCount
        PORT MAP ( Clk          =>   Clock,
                   Res          =>   Clear,
                   H_cntD       =>   hd,
                   H_cntDE      =>   he,
                   H_cntDEB     =>   hb,
                   H_cntDEBC    =>   hc,
                   Rollover     =>   RollClk, -- Output goes to VCount clock
                   Q            =>   Col_OUT );
Click to expand...
 

    BlackOps

    BlackOps

    Points: 2
    Helpful Answer Positive Rating
clk vr

Yes! i did not notice it, thank you! now.. i have some another problem...

here is the error log:
Code: 
Top.vhd(82): (vcom-1136) Unknown identifier "clear".
Top.vhd(81): (vcom-1136) Unknown identifier "clk".
Top.vhd(82): (vcom-1136) Unknown identifier "res".

why is it so? component is declared! and it has behavioral description in the another file of Modelsim project, named HCount.vhd i have a lot of such error statements... what else i could forget?
 

add std_logic_vectors

I think you are not instantiating the component properly....
first you need to declare the component in architecture then instantiate
it after begin.....refer to any vhdl book or xilinx language templates for this....
if problem still persists paste your code...
 

vcom-1136 std_logic

clear should be defined as signal in the top module and i think you might have forgotten to include clk and reset in the component declaration
 

Re: Signal assignment

it seems to me that i declared the components, and all the needed signals. i will paste my final code now. i am also attaching picture of the controller which i want to build.

here goes the code:
Code: 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to add STD_LOGIC_VECTORs

ENTITY VGActrl IS PORT (
Clock:          IN STD_LOGIC;
Reset:          IN STD_LOGIC;
Red:            IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Green:          IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Blue:           IN STD_LOGIC_VECTOR (7 DOWNTO 0);
hs_out:         OUT STD_LOGIC;
vs_out:         OUT STD_LOGIC;
Red_out:        OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Green_out:      OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Blue_out:       OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
column_o:       OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
row_o:          OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END VGActrl;

ARCHITECTURE Structural_VGActrl OF VGActrl IS
    SIGNAL Clk:              STD_LOGIC;
    SIGNAL Res:              STD_LOGIC;
    SIGNAL r:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL g:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL b:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL r_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL g_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL b_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL RollClk:          STD_LOGIC;
    SIGNAL hd:               STD_LOGIC;
    SIGNAL he:               STD_LOGIC;
    SIGNAL hb:               STD_LOGIC;
    SIGNAL hc:               STD_LOGIC;
    SIGNAL vr:               STD_LOGIC;
    SIGNAL vs:               STD_LOGIC;
    SIGNAL vp:               STD_LOGIC;
    SIGNAL vq:               STD_LOGIC;
    SIGNAL h_data_on:        STD_LOGIC;
    SIGNAL v_data_on:        STD_LOGIC;
    SIGNAL h_sync_out:       STD_LOGIC;
    SIGNAL v_sync_out:       STD_LOGIC;
    SIGNAL Col_OUT:          STD_LOGIC_VECTOR (9 DOWNTO 0);
    SIGNAL Row_OUT:          STD_LOGIC_VECTOR (9 DOWNTO 0);
    
    COMPONENT HCount IS PORT (
    Clock:         IN STD_LOGIC;
    Clear:         IN STD_LOGIC;
    Rollover:      OUT STD_LOGIC;
    H_cntD:        OUT STD_LOGIC;
    H_cntDE:       OUT STD_LOGIC;
    H_cntDEB:      OUT STD_LOGIC;
    H_cntDEBC:     OUT STD_LOGIC;
    Q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
    END COMPONENT;

    
    COMPONENT VCount IS PORT (
    Clock:         IN STD_LOGIC;
    Clear:         IN STD_LOGIC;
    H_cntR:        OUT STD_LOGIC;
    H_cntRS:       OUT STD_LOGIC;
    H_cntRSP:      OUT STD_LOGIC;
    H_cntRSPQ:     OUT STD_LOGIC;
    Q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
    END COMPONENT;
    
    COMPONENT SRff IS PORT ( 
    S, R, Clock, Clear: IN STD_LOGIC; 
    Q: OUT STD_LOGIC); 
    END COMPONENT; 
    
    COMPONENT AND3 IS PORT (
    I0, I1, I2: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END COMPONENT; 
    
    BEGIN
    
    -- Horizontal counter interconnection    
        HCOUNTER: HCount
        PORT MAP ( Clk          =>   Clock,
                   Res          =>   Clear,
                   H_cntD       =>   hd,
                   H_cntDE      =>   he,
                   H_cntDEB     =>   hb,
                   H_cntDEBC    =>   hc,
                   Rollover     =>   RollClk, -- Output goes to VCount clock
                   Q            =>   Col_OUT );  
                   
     -- Vertical counter interconnection                
        VCOUNTER: VCount
        PORT MAP ( RollClk      =>   Clock,   -- From Rollover of HCount
                   Res          =>   Clear,
                   V_cntR       =>   vr,
                   V_cntRS      =>   vs,
                   V_cntRSP     =>   vp,
                   V_cntRSPQ    =>   vq,
                   Q            =>   Row_OUT ); 
                   
   -- Here goes interconnection of three SR flip-flops 
                  
        SRFlipFlop1: SRff
        PORT MAP ( hb           =>   S,
                   Clk          =>   Clock,
                   he           =>   R,
                   Res          =>   Clear,
                   Q            =>   h_sync_out );     
    
        SRFlipFlop2: SRff
        PORT MAP ( hc           =>   S,
                   Clk          =>   Clock,
                   hd           =>   R,
                   Res          =>   Clear,
                   Q            =>   h_data_on ); 
                
        SRFlipFlop3: SRff
        PORT MAP ( vp           =>   S,
                   Clk          =>   Clock,
                   vs           =>   R,
                   Res          =>   Clear,
                   Q            =>   v_sync_out ); 
                          
        SRFlipFlop4: SRff
        PORT MAP ( vq           =>   S,
                   Clk          =>   Clock,
                   vr           =>   R,
                   Res          =>   Clear,
                   Q            =>   v_data_on );  
        
        -- Interconnecting RGB signals inside the controller
        
-- Here go 8 AND gates, each producing one red signal for final output
-- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)red in signal
           
        RED_AND1:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(0)         =>   I2,
                   O            =>   r_out(0) );
                                    
        RED_AND2:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(1)         =>   I2,
                   O            =>   r_out(1) );                                 
                          
        RED_AND3:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(2)         =>   I2,
                   O            =>   r_out(2) );                                      
                
        RED_AND4:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(3)         =>   I2,
                   O            =>   r_out(3) );                    
                
        RED_AND5:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(4)         =>   I2,
                   O            =>   r_out(4) );                   
                
        RED_AND6:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(5)         =>   I2,
                   O            =>   r_out(5) );                 
                
        RED_AND7:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(6)         =>   I2,
                   O            =>   r_out(6) );                   
                
        RED_AND8:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(7)         =>   I2,
                   O            =>   r_out(7) );                   
 
 -- Here go 8 AND gates, each producing one green signal for final output
 -- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)green in signal                 
                
        GREEN_AND1:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   r(0)         =>   I2,
                   O            =>   r_out(0) );
                                    
        GREEN_AND2:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(1)         =>   I2,
                   O            =>   g_out(1) );                                 
                          
        GREEN_AND3:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(2)         =>   I2,
                   O            =>   g_out(2) );                                      
                
        GREEN_AND4:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(3)         =>   I2,
                   O            =>   g_out(3) );                    
                
        GREEN_AND5:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(4)         =>   I2,
                   O            =>   g_out(4) );                   
                
        GREEN_AND6:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(5)         =>   I2,
                   O            =>   g_out(5) );                 
                
        GREEN_AND7:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(6)         =>   I2,
                   O            =>   g_out(6) );                   
                
        GREEN_AND8:   AND3
        PORT MAP ( h_data_on    =>   I0,
                   v_data_on    =>   I1,
                   g(7)         =>   I2,
                   O            =>   g_out(7) );
  
  -- Here go 8 AND gates, each producing one blue signal for final output
  -- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)blue in signal 
                    
         BLUE_AND1:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(0)         =>   I2,
                    O            =>   b_out(0) );
                                     
         BLUE_AND2:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(1)         =>   I2,
                    O            =>   b_out(1) );                                 
                           
         BLUE_AND3:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(2)         =>   I2,
                    O            =>   b_out(2) );                                      
                 
         BLUE_AND4:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(3)         =>   I2,
                    O            =>   b_out(3) );                    
                 
         BLUE_AND5:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(4)         =>   I2,
                    O            =>   b_out(4) );                   
                 
         BLUE_AND6:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(5)         =>   I2,
                    O            =>   b_out(5) );                 
                 
         BLUE_AND7:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(6)         =>   I2,
                    O            =>   b_out(6) );                   
                 
         BLUE_AND8:   AND3
         PORT MAP ( h_data_on    =>   I0,
                    v_data_on    =>   I1,
                    b(7)         =>   I2,
                    O            =>   b_out(7) );  
                    
                END   Structural_VGActrl;

please say me whats wrong to this code! thanks!
 

Re: Signal assignment

When instantiating the components, you mixed up (at least partially) formal and actual parameters (left and right side). Ready for a new round in VHDL from the scratch?
 

Re: Signal assignment

hehe...:D what you mean??

what i must change exactly? can u show me as an example how it must be?
 

Re: Signal assignment

COMPONENT HCount IS PORT (
Clock: IN STD_LOGIC;
Clear: IN STD_LOGIC;
Rollover: OUT STD_LOGIC;
H_cntD: OUT STD_LOGIC;
--

-- wrong
HCOUNTER: HCount
PORT MAP (
Clk => Clock,
Res => Clear,
H_cntD => hd,

-- correct
Clock => Clk,
Clear => Res,
H_cntD => hd,
 

    BlackOps

    BlackOps

    Points: 2
    Helpful Answer Positive Rating
Re: Signal assignment

well...again u helped me!

i could compile all the modules, including top.vhd without errors. next step to the real controller will be the frequency division, and pin assignment, then place and route.. will c...

and here is a final version of the above code which compiled without errors:

Code: 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to add STD_LOGIC_VECTORs

ENTITY VGActrl IS PORT (
Clock:          IN STD_LOGIC;
Reset:          IN STD_LOGIC;
Red:            IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Green:          IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Blue:           IN STD_LOGIC_VECTOR (7 DOWNTO 0);
hs_out:         OUT STD_LOGIC;
vs_out:         OUT STD_LOGIC;
Red_out:        OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Green_out:      OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Blue_out:       OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
column_o:       OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
row_o:          OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END VGActrl;

ARCHITECTURE Structural_VGActrl OF VGActrl IS
    SIGNAL Clk:              STD_LOGIC;
    SIGNAL Res:              STD_LOGIC;
    SIGNAL r:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL g:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL b:                STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL r_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL g_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL b_out:            STD_LOGIC_VECTOR (7 DOWNTO 0);
    SIGNAL RollClk:          STD_LOGIC;
    SIGNAL hd:               STD_LOGIC;
    SIGNAL he:               STD_LOGIC;
    SIGNAL hb:               STD_LOGIC;
    SIGNAL hc:               STD_LOGIC;
    SIGNAL vr:               STD_LOGIC;
    SIGNAL vs:               STD_LOGIC;
    SIGNAL vp:               STD_LOGIC;
    SIGNAL vq:               STD_LOGIC;
    SIGNAL h_data_on:        STD_LOGIC;
    SIGNAL v_data_on:        STD_LOGIC;
    SIGNAL h_sync_out:       STD_LOGIC;
    SIGNAL v_sync_out:       STD_LOGIC;
    SIGNAL Col_OUT:          STD_LOGIC_VECTOR (9 DOWNTO 0);
    SIGNAL Row_OUT:          STD_LOGIC_VECTOR (9 DOWNTO 0);
    
    COMPONENT HCount IS PORT (
    Clock:         IN STD_LOGIC;
    Clear:         IN STD_LOGIC;
    Rollover:      OUT STD_LOGIC;
    H_cntD:        OUT STD_LOGIC;
    H_cntDE:       OUT STD_LOGIC;
    H_cntDEB:      OUT STD_LOGIC;
    H_cntDEBC:     OUT STD_LOGIC;
    Q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
    END COMPONENT;

    
    COMPONENT VCount IS PORT (
    Clock:         IN STD_LOGIC;
    Clear:         IN STD_LOGIC;
    V_cntR:        OUT STD_LOGIC;
    V_cntRS:       OUT STD_LOGIC;
    V_cntRSP:      OUT STD_LOGIC;
    V_cntRSPQ:     OUT STD_LOGIC;
    Q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
    END COMPONENT;
    
    COMPONENT SRff IS PORT ( 
    S, R, Clock, Clear: IN STD_LOGIC; 
    Q: OUT STD_LOGIC); 
    END COMPONENT; 
    
    COMPONENT AND3 IS PORT (
    I0, I1, I2: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END COMPONENT; 
    
    BEGIN
    
    -- Horizontal counter interconnection    
        HCOUNTER: HCount
        PORT MAP ( Clock        =>   Clk,
                   Clear        =>   Res,
                   H_cntD       =>   hd,
                   H_cntDE      =>   he,
                   H_cntDEB     =>   hb,
                   H_cntDEBC    =>   hc,
                   Rollover     =>   RollClk, -- Output goes to VCount clock
                   Q            =>   Col_OUT );  
                   
     -- Vertical counter interconnection                
        VCOUNTER: VCount
        PORT MAP ( Clock        =>   RollClk,   -- From Rollover of HCount
                   Clear        =>   Res,
                   V_cntR       =>   vr,
                   V_cntRS      =>   vs,
                   V_cntRSP     =>   vp,
                   V_cntRSPQ    =>   vq,
                   Q            =>   Row_OUT ); 
                   
   -- Here goes interconnection of three SR flip-flops 
                  
        SRFlipFlop1: SRff
        PORT MAP ( S           =>   hb,
                   Clock       =>   Clk,
                   R           =>   he,
                   Clear       =>   Res,
                   Q           =>   h_sync_out );     
    
        SRFlipFlop2: SRff
        PORT MAP ( S           =>   hc,
                   Clock       =>   Clk,
                   R           =>   hd,
                   Clear       =>   Res,
                   Q           =>   h_data_on );  
                
        SRFlipFlop3: SRff
        PORT MAP ( S           =>   vp,
                   Clock       =>   Clk,
                   R           =>   vs,
                   Clear       =>   Res,
                   Q           =>   v_sync_out ); 
                          
        SRFlipFlop4: SRff
        PORT MAP ( S           =>   vq,
                   Clock       =>   Clk,
                   R           =>   vr,
                   Clear       =>   Res,
                   Q           =>   v_data_on );  
        
        -- Interconnecting RGB signals inside the controller
        
-- Here go 8 AND gates, each producing one red signal for final output
-- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)red in signal
           
        RED_AND1:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(0),
                   O            =>   r_out(0) );
                                    
        RED_AND2:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(1),
                   O            =>   r_out(1) );                                
                          
        RED_AND3:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(2),
                   O            =>   r_out(2) );                                    
                
        RED_AND4:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(3),
                   O            =>   r_out(3) );                   
                
        RED_AND5:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(4),
                   O            =>   r_out(4) );                  
                
        RED_AND6:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(5),
                   O            =>   r_out(5) );                  
                
        RED_AND7:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(6),
                   O            =>   r_out(6) );                     
                
        RED_AND8:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   r(7),
                   O            =>   r_out(7) );                  
 
 -- Here go 8 AND gates, each producing one green signal for final output
 -- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)green in signal                 
                
        GREEN_AND1:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(0),
                   O            =>   g_out(0) );
                                    
        GREEN_AND2:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(1),
                   O            =>   g_out(1) );                                
                          
        GREEN_AND3:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(2),
                   O            =>   g_out(2) );                                    
                
        GREEN_AND4:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(3),
                   O            =>   g_out(3) );                   
                
        GREEN_AND5:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(4),
                   O            =>   g_out(4) );                  
                
        GREEN_AND6:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(5),
                   O            =>   g_out(5) );                  
                
        GREEN_AND7:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(6),
                   O            =>   g_out(6) );                     
                
        GREEN_AND8:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   g(7),
                   O            =>   g_out(7) );
  
  -- Here go 8 AND gates, each producing one blue signal for final output
  -- Each gate has three inputs: 1) h_data_on, 2) v_data_on, 3)blue in signal 
                    
        BLUE_AND1:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(0),
                   O            =>   b_out(0) );
                                    
        BLUE_AND2:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(1),
                   O            =>   b_out(1) );                                
                          
        BLUE_AND3:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(2),
                   O            =>   b_out(2) );                                    
                
        BLUE_AND4:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(3),
                   O            =>   b_out(3) );                   
                
        BLUE_AND5:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(4),
                   O            =>   b_out(4) );                  
                
        BLUE_AND6:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(5),
                   O            =>   b_out(5) );                  
                
        BLUE_AND7:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(6),
                   O            =>   b_out(6) );                     
                
        BLUE_AND8:   AND3
        PORT MAP ( I0           =>   h_data_on,
                   I1           =>   v_data_on,
                   I2           =>   b(7),
                   O            =>   b_out(7) );    
                    
                END   Structural_VGActrl;
 

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