VGA Horizontal counter, Behavioral VHDL code

vga vhdl

Hello,

i am trying to code the behavioral VHDL model of the VGA Horizontal counter, from the Enochs book. (as some people have adviced me to make simple things in behavioral model. And i will connect all elements in structural code in the Top source file). Please take a look at the picture of the schematic of Horizontal counter from the book.

here is my code:


meaning of this counter is, when it reaches 800, the Rollover is 1, and it begins counting from 0 again.. so.. as you can see i have combined code of 10 bit counter to fit my problem, and removed unused Count and Load inputs. Because HCount elemtn will have only: Clock,CLear,H_cntD,H_cntDE,H_cntDEB,H_cntDEBC,Rollover, and 10 bit Q outputs

please could you say me is this code ok? if no could u please fix the errors.

during compile in Modelsim it gives me this:

But i dont understand what it wants to say with this..

thank you

vhdl vga

when writing a bus should be like this b"00001111" or x"ffff" or b"0_1_0_1"

you put '

vga vhdl code

Additionally, the B base specifier can be omitted, cause it's default.

vhdl code for vga

well i tried putting " instead of ' but nothing worked... any ideas? where exactly u want me to put it? i did put it after B.. also tried to put it like H_cntD <= "1";

my code:

errors:

vga +vhdl

Yes, in your first example you had H_cntD <= '1', which is correct syntax for assignment, now you have H_cnt => "1", which implies two syntax errors in one line. Please use the original expression. For bits, unlike bit vectors a constant value uses a single quote and the assignment operator is <=.

behavioral vhdl

WELL, OK now i have this:


and the errors now are:

what does it mean now? as u see, all in line 39... something is wrong there... but what exactly?.. :?:

Added after 51 minutes:

something is wrong to this line:
H_cntDEBC <= '1' & Rollover <= '1' & value <= (OTHERS => '0');

is it ok to assign multiple things like i did?

vhdl near ): expecting identifier

H_cntDEBC <= '1'; Rollover <= '1'; value <= (OTHERS => '0');

near $ expecting identifier

now that worked! thank u for help!

std_logic_vector rollover

hi,
please check this code , i written this code for the HP7540 MONITOR.........
I AM NOT GETTING WHATS WRONG IN THIS PLEASE HELP ME ......THANKS IN ADAVANCE





LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


entity test_vga1 is
port ( clk : in std_logic;
reset : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
blank_n : out std_logic;
dac_clk : inout std_logic;
Pclk : out std_logic;
blank_out : out std_logic;
sync_n : out std_logic );
end test_vga1 ;


architecture VGA of test_vga1 is

signal Vclk : std_logic;
--signal Pclk :std_logic;
signal Osig : std_logic;
signal Hcount : std_logic_vector(21 downto 0);
signal Vcount : std_logic_vector(21 downto 0);
signal B1count: std_logic_vector(21 downto 0);
signal Bcount : std_logic_vector(21 downto 0);
signal tot_count:std_logic_vector(21 downto 0);
signal hblank : std_logic;
signal Vblank : std_logic;
signal blank : std_logic;
signal h2blank: std_logic;
signal v2blank: std_logic;
signal trial_data :std_logic_vector(23 downto 0);
type data is array (0 to 2699 )of std_logic_vector(23 downto 0) ;



component pll1
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

--constant picture :data :=(




signal lsrt :std_logic;

begin
trial_data<="111111110000000000000000";
lsrt <= not(reset);

--bit0: PLL1 port map ( areset =>lsrt , inclk0 => clk, c0=>Pclk, locked =>Osig );
bit1: pll1 port map( areset =>lsrt , inclk0 => clk, c0=>dac_clk, locked =>Osig );

Pclk<=dac_clk;

--Pllclk <= Pclk;

hsyn_corocess (clk, reset) is
begin
if reset='0' then
Hcount <="0000000000000000000000" ;
hsync <='1';
elsif(clk'event and clk='1') then
if (Hcount < "0000000000000001101110")then -- and Hcount < "0000000000011010010000") then
hsync <= '1';
else
hsync <= '0';
end if;
if Hcount <"0000000000011010010000" then
Hcount <= Hcount+'1';
else
Hcount<="0000000000000000000000" ; --"0000000000000000000000" ;
end if;
end if;
end process;

vsync_tim: process(clk,reset ) is

begin
if reset='0' then
Vcount <="0000000000000000000000" ;
vsync<='1';
elsif(clk'event and clk='1') then
if (Vcount < "0000000010100101101000" ) then --and Vcount< "0110010010111110101000") then
vsync<= '1';
else
vsync<='0';
end if;
if Vcount < "0110010010111110101000" then --if Vcount > 16784 then
Vcount<= Vcount+'1';
---Vcount:=0;
else
Vcount<="0000000000000000000000" ;
end if;
end if;
end process;



--
--
--hblank_sig: process(clk, reset) is
-- begin
-- if reset='0' then
-- Bcount<="0000000000000000000000";
-- B1count<="0000000000000000000000";
-- tot_count<="0000000000000000000000";
-- blank<='1';
-- elsif(clk'event and clk='1') then
-- if (tot_count<"0000011111101010011010")then
--
-- if(Bcount > "0000000000000010100111" and Bcount < "0000000000101101000010") then
-- h2blank<='0';
-- else
-- h2blank <='1';
-- end if ;
--
-- if Bcount < "0000000000101101000010" then
-- Bcount<= Bcount+1;
-- else
-- Bcount<="0000000000000000000000";
-- end if;
--
--
-- elsif(tot_count<"0111001011101001000010")then
-- if( (tot_count < "0000011111101010011010") and tot_count < "0111001011101001000010")then
-- h2blank<= '0';
-- end if;
--
-- if tot_count < "0111001011101001000010" then --if count> 16784 then
-- tot_count <= tot_count+1; -- blank<= '0';
-- else
-- tot_count<="0000000000000000000000"; --count:=count+1;
-- end if;
-- end if;
--
-- end if;
-- blank_n <=h2blank;
-- blank_out<= h2blank;
--
-- end process;
--
--
--
--
--
--
--







hblank_sig: process(clk, reset) is
--subtype min is integer range 0 to 1882690 ;
--variable count: integer;
begin
if reset='0' then
Bcount<="0000000000000000000000";
B1count<="0000000000000000000000";
blank<='1';
elsif(clk'event and clk='1') then
if(Bcount > "0000000000000010100111" and Bcount < "0000000000101101000010") then
blank<='0';
-- elsif (Bcount > "0000011111101010011010" and Bcount < "0111001011101001000010") then
-- blank<='0';
else
blank <='1';
end if ;
-- if Bcount < "0000000000101101000010" then
-- Bcount<= Bcount+1;
-- else
-- Bcount<="0000000000000000000000";
-- end if;
-- if (Bcount>"0000011111101010011010" and Bcount< "0111001011101001000010") then
-- blank<= '0';
-- else
-- blank<='1'; --count:=1;
-- end if;

if Bcount < "0000000000101101000010" then --if count> 16784 then
Bcount<= Bcount+1; -- blank<= '0';
else
Bcount<="0000000000000000000000"; --count:=count+1;
end if;
end if;
end process;





--vblank_sig: process(clk, reset) is
-- --subtype min is integer range 0 to 1882690 ;
-- --variable count: integer;
-- begin
-- if reset='0' then
-- B1count<="0000000000000000000000";
-- blank<='1';
-- elsif(clk'event and clk='1') then
-- if (B1count>"0000011111101010011010" and B1count< "0111001011101001000010") then
-- blank<= '0';
-- else
-- blank<='1'; --count:=1;
-- end if;
-- if B1count<"0111001011101001000010" then --if count> 16784 then
-- B1count<= B1count+1; -- blank<= '0';
-- else
-- B1count<="0000000000000000000000"; --count:=count+1;
-- end if;
-- end if;
-- end process;
--
blank_n <= blank;
sync_n <='0';
blank_out <= blank;

--

data_tranfer: process (reset, dac_clk) is
variable count: integer :=0;
begin
if reset='0' then
red <="00000000";
green <="00000000";
blue <="00000000";
elsif dac_clk='1' and dac_clk'event then
--if count < 307200 then
---------trial_data <= picture(count);
red <= trial_data (7 downto 0);
green <= trial_data (15 downto 8);
blue <= trial_data (23 downto 16);
count :=count+1;
-- end if;
end if;

end process;



end VGA;

behavioral code vhdl integers

for which chip are u writing the code? honnaraj?

vhdl coding for vga

You should tell, what kind of unexpected results you get. It' simple enough to check it's operation with an easy operatable simulator. I think it's compiled with Quartus according to the PLL module syntax, you could post e. g. simulation result and point out, what seems to be wrong.

vga horizontal counter, behavioral vhdl code

My little Verilog example may be helpful to someone. It generates a simple animated 800x600 pixel display using a Xilinx/Digilent Spartan-3 Starter Kit:
#528046