Some doubts on Dual Slope ADC

Hi friends,

What is the frequency range of input signals it is normally used for.

how do we find the integration period.is it related to the input signal frquency.


Please help.
Thanks

Hello,

integration period is actually related to signal frequency, cause i supresses frequencies with a period equal to integration period and it's integer mutiples. It has been often used with 100 ms or 20 respectively 16.7 ms period to suppress mains interferences. Cause it needs a time-to-digital converter with sufficient relative solution, it's not suitable for short integration periods.

Has been replaced by SD-converters in most applications in the last years. For high accuracy application, dual-slope linearity is limited by capacitor loss factor.

Regards,
Frank

See now the thing is the input to the dual slope comes from another amplifier which already removes the mains interference noise as you suggested. So considering that i have an input signal of lets say 1 khz frequency , what would be the integration period for this signal.assuming 12 bits resolution.

from what i understand after reading ken martin book the integration period should be multiple of 1khz .That is 1/(10*1khz)= 100us, where the factor 10 is the multiplying factor i took.

This should be equal to RC from which we calculate the values.

TO calculate the clock frquency of the counter we have to equate 100 us to
2^N*Tclk where N=12 bits

from this we get Tclk for the counter as 2^N*Tclk=100us
Tclk=24.4ns or the Fclk=40.96Mhz

Am i right in the above calculations.


Thanks for your help