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Can any body tell me what does LEF / DEF contains?

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vikramc98406

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As far as I know
LEF contains Boundary, pins, Blockage layer info
DEF used alternative for GDSii for standard cells.

Can any body give more info on these w.r.t
SDF extraction and Layout verification checks
 

Is ur question correct ?? SDF extraction??? wt do u mean by this??

SDF contains delay values yaar not resistance and capacitance values...

Layout verification check is something where u need to check for the design rules such as spacing rule,opens ,shorts and so on I mean where ur getting opens and where ur getting shorts and so on...

Don't forget to push help button
Bye take care
 

vlsitechnology,
pls giv me more details of what LEF and DEF contains

while extraction SPEF (for RC values) what is the input?
what are taken for signal/power net extraction (DEF/LEF)

What are the inputs for Layout verification.
if LEF/DEF, how are these mixed to do verification

Hope i am clear this time....
 

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