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Help for implementing parallel adder

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platopathrose

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hai friends,
I am new to this fpga design and all.
i am doing an adder now which is
x = z + a1 + a2 + a3 + a4;
it is taking a more delay,
i thought of implementing a tree type adder, which is like

a12 = a1 + a2;
a34 = a3 + a4;
x = z+a12 + a34;

will this work?.. or should i use soem clocking parameters?..

expecting your valuable suggestions:)
 

Yes it will work. But the delay increases proportionately with the number of levels in turn number of Gate braches, as shown in the diagram..There are many ways you can implement an adder..half adder, full adder, but if the delay should be less 'Carry look ahead adder' will be the best and simple choice

It will add n bit m input system in an efficient way by generating the carry before it is actually generated by the normal adder. As it is generating the carry ahead, nth adder need not wait for n-1th carry, so the system will be fast..
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Hello,

basically the HDL compiler should be able to find appropriate structure for your adder. At a certain level of complexity, a pipelined design may be necessary. But it depend strongly on necssary operation speed respectively timing constraints for input and output signals.

Regards,
Frank
 

thanks a lot for your advices...
i am trying to go ahead with this...-:)...

if u have any further opinions.. plz do let me know

regards...
Plat
 

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