Mercury
Member level 3
vhdl prescaler
Hi!
I have written the simplest possible VHDL prescaler ( Xilinx webpack 5.2, 9500 CPLD ).:
entity prescaler is
Port (
rst: in std_logic;
clk_in: in std_logic;
clk_out: out std_logic
);
end prescaler;
architecture presc of prescaler is
signal count: std_logic_vector(9 downto 0);
begin
p00: process(rst,clk_in)
begin
if rst = '0' then
count <= "0000000000";
elsif clk_in'event and clk_in = '1' then
count <= count + 1;
end if;
end process;
clk_out <= count(9);
end presc;
Now, take a look at the RTL Schematics. The clk_out ouput is not even connected, however it is recognised as a pin. What is going on here???, can anyone please help?
Best Regards
George Mercury
Hi!
I have written the simplest possible VHDL prescaler ( Xilinx webpack 5.2, 9500 CPLD ).:
entity prescaler is
Port (
rst: in std_logic;
clk_in: in std_logic;
clk_out: out std_logic
);
end prescaler;
architecture presc of prescaler is
signal count: std_logic_vector(9 downto 0);
begin
p00: process(rst,clk_in)
begin
if rst = '0' then
count <= "0000000000";
elsif clk_in'event and clk_in = '1' then
count <= count + 1;
end if;
end process;
clk_out <= count(9);
end presc;
Now, take a look at the RTL Schematics. The clk_out ouput is not even connected, however it is recognised as a pin. What is going on here???, can anyone please help?
Best Regards
George Mercury
