Questions about pipelined array multiplier

multiplier

Hi, I want to design one Baugh-Wooley pipelined array multiplier as this figure. I have completed the part of FA with and gate now, but I don't know how to realize the latch part for the partial products.

I mean, if I want to use "generate" statement, how to write the code so it can select appropriate number of latches for the given partial product? i.e. there are 8 latches for P0, 7 latches for P1. Especially for P5~P9, it becomes more inconvenient. Thank you in advance.

pipelining of multiplier

I have a code for pipeline multiplier. I was using it in a fast reconfiguration platform for some special porouse computing. If you want it write me. i will upload it.
But generaly "Generate Statement" is not good choice for synthesis. Try another way!

pipelined multiplier verilog

Thank you for your source. I think i need it.

array multiplier verilog

Hi Zerox100, I've had good luck using Verilog 'generate' in my Xilinx ISE projects. It has saved me many hours of work. Have you had bad luck with it?

array multiplier

yes. especially nested generate sttement! and of course it depends on how you would generate. If its a simple circuit it's OK.
Any way it's my code:
If it wouldn't help you write me what do you want to do exactly. I will help you.
---------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

entity pipelined_multiplier is

generic (size : integer := 16; level : integer := log(size));

port (
a : in std_logic_vector (size-1 downto 0) ;
b : in std_logic_vector (size-1 downto 0) ;
clk : in std_logic;
pdt : out std_logic_vector (2*size-1 downto 0));
end pipelined_multiplier ;

architecture exemplar of pipelined_multiplier is
type levels_of_registers is array (level-1 downto 0) of
unsigned (2*size-1 downto 0);
signal a_int, b_int : unsigned (size-1 downto 0);
signal pdt_int : levels_of_registers;

begin
pdt <= std_logic_vector (pdt_int (level-1));

process(clk)
begin
if clk'event and clk = '1' then


a_int <= unsigned (a);
b_int <= unsigned (b);

pdt_int(0) <= a_int * b_int;
for i in 1 to level-1 loop
pdt_int (i) <= pdt_int (i-1);
end loop;
end if;
end process;
end exemplar ;

multiplier with pipeline using verilog code

Ahh, VHDL. I'm using Verilog with XST. I've filled up some pretty big FPGAs with Verilog 'generate' logic without much trouble. I don't recall ever using nested generate loops, however, so maybe I haven't triggered the problems you've seen. Or maybe the Verilog compiler doesn't have that bug.

If you can document the nested generate problem, you should send it to Xilinx so they can fix it. They usually fix my reported bugs, eventually.

pipelined multiplier fpga

Are you sure! You used Generate statement in Verilog!!!! I haven't heard any thing about Generate statement in verilog!!! Can you share your code?

verilog pipelines with generate statements

'Generate' was added to the Verilog language in 2001.

Sorry, I don't have any small interesting projects that uses 'generate'. I can't show my big projects because they were done for a client. However, you can search your XST User Guide for the keyword 'endgenerate', and you'll find a few small (unexciting) examples.

For more info, grab a copy of IEEE Std 1364-2005 (the current Verilog language standard), or any modern Verilog textbook that includes Verilog 2001.

verilog pipelined multiplier

Can you kindly say us what is your project?
any way This the verilog code for pipelined multiplier. I hope it help you.
----------------------------------------------------
module pipelined_multiplier ( a, b, clk, pdt);
parameter size = 16, level = 4;
input [size-1 : 0] a;
input [size-1 : 0] b;
input clk;
output [2*size-1 : 0] pdt;
reg [size-1 : 0] a_int, b_int;
reg [2*size-1 : 0] pdt_int [level-1 : 0];
integer i;

assign pdt = pdt_int [level-1];

always @ (posedge clk)
begin

a_int <= a;
b_int <= b;
pdt_int[0] <= a_int * b_int;
for(i =1;i <level;i =i +1)
pdt_int <= pdt_int [i-1];
end
endmodule

nested generate verilog

Hi Zerox100, my big FPGA projects did focused beamforming of transmit and receive antenna arrays.
They used many parallel processing sections, so the 'generate' statement greatly shortened the Verilog code.