vinodkumar
Full Member level 5
confused
Hi everybody,iam new to System Verilog,iam comfortable with VHDL and Verilog.i have done few projects in both.
now i want to develop verifcation models and test cases for those.
i have gone thru some examples of SV in the internet,
than i confused when to use
Module
Program
Task
Function
interface
class
i saw some docs but not clear with fundas
iam looking for some docs which states basics.waiting for replies.
Hi everybody,iam new to System Verilog,iam comfortable with VHDL and Verilog.i have done few projects in both.
now i want to develop verifcation models and test cases for those.
i have gone thru some examples of SV in the internet,
than i confused when to use
Module
Program
Task
Function
interface
class
i saw some docs but not clear with fundas
iam looking for some docs which states basics.waiting for replies.