attribute LOC - help needed

attribute LOC of

HI All,
Iam trying to allocate the FPGA pins to my nets in the VHDL
Iam using the attribute LOC commands
just like:

attribute LOC : string;
attribute LOC of clock : signal is "p91";

that's ok and it's working but when iam trying to allocate pins for a
std_logic_vector here is the problem

If i -for example - defined in my entity
data : inout std_logic_vector(15 downto 0);
and tried to use the attribute for assigning pin locations for my data bus
using :
attribute LOC : string;
attribute LOC of data(0) : signal is "p133";
attribute LOC of data(1) : signal is "p137";
.
.
It doesn't work and compiler give me error
I think that the error in the form of the bit_vector
I have tried to write data<0> instead of data(0) but it didn't work also

can any body help

Re: attribute LOC of

Just curious :roll:

Why do you want to LOC your pins in your RTL?

I guess you knoe that you can do it using a UCF (for example) and instead of using two lines

attribute LOC : string;
attribute LOC of clock : signal is "p91";

you use one

NET "clock" LOC = "P91";

And if you want to reuse your design in another board/project you have to modify your RTL again, resynthesize and rebuild it, if it is seriouslly big we could be talking about 3-4 hours of building time...using the UCF you only rebuild it, you don't have to create the synthesis netlist again.

I hope it helps,
-maestor

Re: attribute LOC of

You are completely right but iam designing an develpment board and i want to attach some sample codes with this board so i want this code to be read only and it's just to make the user to get started with the kit ..
that's all