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What will synthesizer do when there is a race condition?

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kelvin_sg

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I was studying codes written by others, one style is confusing me,

Code: 
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
   dat <= 10'd0;
end
else begin
   if (sel0) begin
      dat <= dat0;
   end
   if (sel1) begin
      dat <= dat1;
   end
end
end

The code is from a well known IC design companies, whom we outsource
RTL design to.

Will synthesizer do well with this? I was taught not to use this style previously.
 

Not a great way to code , but it will be implemented as a mux (or equivalent) followed by a flop (with asynchronous reset) ...
However there might be an inferred latch - due to the absence of an else statement for the if statement

How do you see the race condition happening ???
 

vinayshivakumar said:
Not a great way to code , but it will be implemented as a mux (or equivalent) followed by a flop (with asynchronous reset) ...
However there might be an inferred latch - due to the absence of an else statement for the if statement

How do you see the race condition happening ???
Click to expand...

so it's not called a race.. :!: but I am concerned with condition when "sel0&sel1 == 1'b1"

AFAIK Simulation-wise, it will behave like the table, but I am not sure how
synthesizer will deal with it. That's why I ask.
The code will be used in both design compiler and Cadence's RTL compiler.



sel0 sel1 dat
0 0 dat(-1) <-unchange
1 0 dat0
0 1 dat1
1 1 dat1


always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
dat <= 10'd0;
end
else begin
if (sel0) begin
dat <= dat0;
end
if (sel1) begin
dat <= dat1;
end
end
end
Click to expand...
 

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